Issue



Substrate innovations for the mobile application processor market


11/01/2011







From process technologies, to materials innovation, to pricing models, many innovations have been introduced by substrate suppliers to enable the growth of FC CSP in the mobile market.

Abram Castro, Texas Instruments, Dallas, TX USA


Integrated circuit (IC) package engineers are challenged to provide miniaturized, integrated, electrically/thermally managed, and cost-reduced solutions for next-generation silicon. While improvements in bond wire, mold compounds and die attach adhesives have kept the wire bond market moving forward, it is the emergence of the versatile organic substrate that is enabling the explosive growth of flip-chip interconnect in advanced packaging applications.


Substrate-based packaging has its roots in the mid-1980s and 90s in ceramic-based flip-chip. Though limited to the high end of the market, it created an infrastructure of designers, materials suppliers, and process expertise in Japan. Leveraging this infrastructure, companies such as Motorola and Amkor initiated a transition to organic substrates in ball-grid array (BGA) packaging in the early and mid-90s. The advantages of the lower cost, design flexibility, and multiple sourcing options drove substrate adoption into wire bonded PBGA, chip-scale packaging (CSP) and module-based packages, and eventually replaced its ceramic predecessor in flip-chip BGA (FC BGA). These packages proliferated rapidly in industrial, computer, gaming and consumer markets, and continue to thrive today with an estimated total available market (TAM) for organic substrates of ~$8B by the year 2014 (Prismark Partners).


Drivers for organic substrates


The recent emergence of the smart phone and tablet market is creating a new driver for organic substrates ??? the flip-chip CSP (FC CSP) package. Driven by mobile application processors, the FC CSP package is roughly 25-35% of the size of its FC BGA predecessor and is being called upon to deliver high end performance and feature sets at a mass consumer cost. These demands include the challenge to maintain electrical integrity at high speed (GHz), facilitate thermal dissipation (multi-watt), and drive miniaturization under the steady progress of Moore's Law.


But unlike the PC market before it, the form factor reduction demands of hand-held and mobile consumer environments have presented new challenges for FC CSP implementation. These include: 1) distribution of high pin counts (>800) in small form factors, 2) providing mechanical integrity in thin (sub-1.0mm) formats, including package stacking), and 3) maintaining reliability and integrity in varied consumer environments. These challenges must invariably be managed by the package substrate (see Fig. 1).










Figure 1. Typical FC CSP cross-section.

Meeting the density challenge


FC CSP packaging leverages two design approaches: full array flip-chip or peripheral flip-chip.


The challenge for both approaches is to "fan out" silicon pitch to match the coarser package level pitch. As in FC BGA, fine-line lithography is a must have, but in mobile markets an extremely limited X/Y footprint creates the additional problem of "via density."


Vias are the electrical and thermal conduits that allow connection from the device side of the package to the termination side. As demand for multiple power domains, interfaces, and higher IO counts increases, via counts have exploded. The traditional method of "drilling" through a substrate with mechanical bits no longer works because of limited via size (+100??m) and via-to-via pitch (200??m). For advanced silicon nodes these design rules become prohibitively restrictive.


To meet the via density challenge, substrate vendors have developed "laser thru hole" vias in cores to replace mechanical drilling. Laser via technology is not new, having been used as the via formation method in build up applications for 10+ years. But core thickness in FC BGA made use of a laser too slow and cumbersome. In FC CSP, dielectrics are much thinner and both reinforcing glass fabrics and laser processing equipment have been optimized to deliver cost effective drilling for the densest of via pitches. Today, several application processors w/laser core vias as small as sub-100??m pitch are in mass production ??? a density improvement of over 40%.


Mechanical considerations


Two trends in mobile applications have combined to push FC CSP mechanical performance ??? thinner phones, and package-on-package (POP) stacking. Figure 1 shows the stack height of an FC CSP package is limited to its ball, substrate, and silicon thickness, thus with few opportunities for reduction. Both wafer thinning (<100??m) and ball reduction (~200??m) have seemingly reached their manufacturing and reliability limits, placing future emphasis for thickness reduction squarely on the package substrate. Further complicating the challenge is the need for the substrate to provide mechanical rigidity for successful surface mount operations.


To drive thinner solutions, substrate material vendors have focused on the development of ultra-low CTE materials. Ultra-low CTE materials (CTE of <6ppm) are designed to help match substrate and silicon mechanical properties, thus reducing overall package stress. Lower stress means less warpage, and consequently the substrate is able to be "thinned" and still meet the warpage performance of thicker, higher CTE counterparts. To enable processing of these thinner cores, investments by substrate vendors in the thin core handling equipment and process lines are essential.


Reliability and test challenges


New via technologies, new substrate materials, thinner substrate cores and new FC interconnect schemes have created new challenges for reliability and test engineers. Combined with the acceleration of product life cycles (eliminating long development cycles), first-pass reliability success is a "must." As such, substrate suppliers and materials sources have been forced to rethink how new materials and processes are introduced.


To meet this challenge, IDMs and their substrate supply partners are investing in new types of failure modes and effects (FMEA) -based product development, "hammer tests," modeling techniques, and monitoring techniques to achieve first time qualification success. These tests have been designed to closely mimic real world application requirements and quickly isolate potential failure modes as substrate houses quickly learn to mimic reliability and test methods of their semiconductor customers.


Cost


Despite recent performance gains, substrates are not immune to the cost pressures of the mobile market. The substrate is by far the highest percentage of the materials cost in the package, on average comprising 40???60% of the bill of materials (BOM). Yield curves, utilization rates and process efficiencies are being fully exploited to drive cost along with a new emphasis on delivery format. Historically, a substrate was shipped in a format predicated by assembly needs. But today's substrate manufacturers are partnering with their assembly customers to customize configurations in order to minimize cost. Innovations in strip configuration, small body singles and custom substrate matrices combine the needs of both assembly and substrate partners.


Future


Many innovations have been introduced by substrate suppliers to enable the growth of FC packages in the mobile market. From process technologies to materials innovation to pricing models, the substrate industry is transforming itself to meet these challenges and will continue to do so in the future.


Abram Castro received his EE from Texas A&M U. and is the Platform Materials Manager for Texas Instruments SC Packaging team, 13020 TI Boulevard, Dallas, Texas, 75265; ph.: 214-567-7546; email a-castro@ti.com.


Solid State Technology | Volume 54 | Issue 10 | November 2011


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