EUV OPC flow optimization for volume manufacturing


Executive Overview

Extreme ultraviolet (EUV) lithography is a leading contender for patterning of the 2X node memory and 14nm logic manufacturing and will provide significant relaxation in k1 factor versus existing 193nm lithography. However, EUV does add additional difficulties to mask synthesis flows such as across-slit shadowing variation, across-reticle flare variation, new resist effects, and significant increases in file size. This article will investigate EUV-specific issues and solution options for a production mask synthesis flow, including different correction and flow automation approaches. Improved methods help enable EUV optical proximity correction (OPC) tapeout flows to achieve comparable or better metrics than existing 193nm lithography flows.

Kevin Lucas, Jonathan Cobb, Johnny Yeap, Munhoe Do, Synopsys Inc., Mountain View, CA, USA

The 14nm logic node will have features at a minimum half-pitch of approximately 24 to 28nm, and the industry's first high-volume manufacturing (HVM) for these nodes will likely start in 2015. Several 1.35NA 193nm optical lithography options have been considered for patterning at the 14nm node, including double patterning, triple patterning, and self-aligned double patterning. Another option is to lower the light wavelength to 13.5nm with 0.32NA EUV scanners. This enables relatively high k1 lithography and may offer the resolution required for the 10nm device generation by increasing projection system numerical aperture (NA).

With leading semiconductor manufacturers receiving beta EUV scanners in 2011-12, the pace of EUV integration development will rapidly accelerate. Therefore, the demand for accurate and fast EUV OPC software to synthesize reticle patterns will substantially increase in the near future. However, there are several flow issues to resolve before OPC is ready to meet integration and production needs. This article will examine those flow issues and some state-of-the-art solutions [1].

Introduction to EUV OPC

There are several new physical effects that need to be considered in EUV OPC. Several of the most important are:

  • Long-range flare (scattered light from roughness in the lens elements), which varies in intensity across the exposure field [2-4];

  • Long-range reflected light from the large EUV mask absorber regions at the edges and corners of the exposure field, which are in between the reticle bladed-off region and the desired exposure area [5];

  • Long-range exposure position-dependent and scan-dependent asymmetric flare effects modified by flare apertures in the scanner [6,7]; and

  • Shadowing effects from the interactions of mask absorber topography and the non-normal main optical exposure angle which varies across the reticle [3].

There are a number of technical challenges in adapting OPC for long-range effect correction. The radius over which flare and shadowing effects are calculated may be in the 20+mm range compared to the typical OPC kernel range of 1-2??m. Brute-force methods of incorporating these long-range effects into OPC will not be fast enough to meet the turn-around-time (TAT) requirements of mask synthesis flows. For flare, clever approximations are required to speed up the computations while achieving accuracy requirements of approximately 0.10% 1?? flare error for development applications and 0.05% 1?? flare error for production. Additional reticle scale and scanning-dependent flare and shadowing effects must also be accurately encapsulated into compact models, which can run quickly on extremely large layouts.

EUV mask synthesis full flows and issues

There are several major OPC issues that result from correction of significant long-range physical effects. One issue is that each chip placement is now lithographically distinct and must receive a unique OPC modification. For reticles with only one or a few placements of a very large chip, the impact on OPC is not great. However, for the typical case where there are many placements of a medium-sized or small chip, the impact on OPC is very large, i.e., many chips will have to be OPC processed in order to define a reticle. A related issue is that we can no longer assume multiple placements of a single cell inside a chip design are lithographically identical. This is due to the different magnitudes of flare and shadowing effects across each individual chip placement. The combination of these two issues results in the requirement that OPC must produce a final post-OPC data file with little or no design hierarchy (i.e., flat) that covers the entire exposure field of the reticle. The resulting TAT and post-OPC file size will then be much larger than is typically handled with OPC for 193nm lithography.

Figure 1. Typical EUV mask synthesis flow containing pre-OPC, OPC, OPC verification, MDP and EUV mask defect avoidance steps. Sample graphical examples for each flow step are shown at right. [1] Used with permission of SPIE.

A flow diagram of a typical EUV mask synthesis total flow is shown in Fig. 1. This flow includes the following steps: pre-OPC (biasing for device and process considerations); reticle layout creation (placement of individual chips in the reticle field); OPC (including both model-based flare and model-based shadowing compensation); full model-based OPC verification; MDP (mask data prep and fracture to create the final reticle data); FTP (to either an internal or external maskshop); and mask defect avoidance (shifting the layout pattern relative to the mask blank to avoid irreparable EUV buried mask defects from printing on a critical layout feature [8]). The TAT to meet fab cycle-time goals for the same advanced mask synthesis flow are typically 12 to 24 hours for OPC, OPC verification and MDP/fracture steps; and less than a few hours for other steps. Because of the across-reticle effects that need to be handled in EUV, traditional OPC methods may lead to missing these TAT goals by many hours or even by several days.

OPC improvements for EUV

Significant improvements are needed to enable EUV mask synthesis flows to meet overall TAT requirements. Improvements in TAT can be obtained by optimizing the methods used to compute new EUV physical effects. To illustrate this, several different methods were investigated for EUV flare computation across the reticle (e.g., [1,2, 9-10]) and a method implemented that exhibited both high accuracy and speed. Accuracy was benchmarked against a rigorous lithography EUV simulator's full-chip flare computation for different layouts. The flare error between the OPC model computed flare and the rigorous simulator was found to be lower than the production target accuracy of 0.05% 1?? for a scanner with a flare TIS of 4.5%. This method of flare calculation can enable recalculation of the flare map in just a few minutes from a density map.

Figure 2. Example of a new mask-based shadowing compensation methodology. The different wafer contours across the reticle slit for the same input mask pattern can be clearly seen. [1] Used with permission of SPIE.

Increasing speed without sacrificing model accuracy is possible by optimizing long-range shadowing modeling. Figure 2 illustrates a new faster mask-based shadowing compensation methodology. This method enables fitting both the ideal shadowing bias across the reticle scan and empirically observed process and tool specific characteristics. These shadowing model speedups and accuracy enhancements also benefit the full-reticle, full-model-based OPC verification step.

New EUV mask synthesis flows to improve TAT

The TAT improvements described above offer significant benefits for individual components in the mask synthesis flow. However, further improvements are necessary to make up for a) the large increases in TAT flow expected due to the full flattening of reticle-level data as input to OPC; and b) the very large data files, which take considerable time to be passed between components in the flow. Another problem with the large data files in EUV is that any steps in the flow that are not highly distributable (across many processor cores) quickly become bottlenecks and begin to dominate the overall TAT. MDP/fracture tools do not distribute linearly to many hundreds of processors, as OPC does. In addition, read-in/out steps of tools are generally poorly distributable. Therefore, as data volumes continue to rise into multiple terabytes of data per layer [11], lower scalability steps can lead to significant flow delays. To counteract these issues, a parallelized combined OPC + MDP flow for EUV can be implemented that utilizes the massive parallelization capability of data cells/templates that have finished all OPC and cell context updating. Completely finished cells/templates can be passed in a pipeline to start MDP/fracture modification well before the full OPC job has completed. This effectively enables massive parallelization of read-in/out and MDP/fracture steps (Fig. 3).

Figure 3. Parallelized combined component flow for EUV. The flow utilizes massive parallelization of cells/templates of data that have finished all previous component processing and cell context updating. Cells/templates completely finished by the previous component can be passed in a pipeline for modification by the next flow component to start well before the previous component has completed the entire layout. [1] Used with permission of SPIE.

Experimental results show sizeable TAT savings with such a parallel approach [10]. For a large (600mm2 area, 16nm logic) test case running in standalone mode, MDP took approximately 16hrs. Running the same test case in parallel mode took exactly 1 hour ??? 15-hour savings in reticle data availability for mask write. In a moderate sized 3X node DRAM chip example running in standalone mode, MDP took 1.5 hours, but running the same test case in parallel mode took only 3 minutes. As this DRAM chip would be repeated 15 times in the reticle field, the estimated TAT for a full reticle case is 22.5 hours vs. 45 minutes, achieving a savings of over 21hrs in data availability for mask write. TAT savings will further increase for denser 10nm node logic and 2X/1X node memory cases.

Unfortunately, EUV's large post-OPC and post-fracture file sizes causes the FTP transfer between different groups within a company or to the mask shop to take many hours of user time. Currently, FTP of a 40nm mask set (all layers) that is 1 terabyte (TB) post-fracture often takes 12hrs on a fast FTP connection to the mask shop. Thus, the FTP step alone for a single 1X node RAM single layer file of 3.3TB would take more than 36hrs. To meet these requirements, existing MDP/fracture functionality can be reused, parallelizing the FTP of huge post-fracture data files well before fracture has completed. Results on very large fractured files show that FTP time can be reduced to less than one hour with this parallel method.


Several new physical effects are impacting EUV OPC and mask synthesis flows. The impact of these effects on accuracy and TAT of flows was evaluated, especially the large increase in data file sizes for EUV mask synthesis and the risk this poses for meeting strict modern mask synthesis flow TAT requirements. After review of several options for improving the TAT and accuracy of individual flow components and the entire flow, results show that EUV flows can be optimized to meet stringent production TAT and accuracy requirements of future nodes.


The authors would like to thank the following people for their helpful work and support:

Hua Song, Lin Zhang, Jim Shiely, Robert Lugg, Yan Ping, Stephen Jang, Lena Zavyalova, Lantian Wang, Kunal Taravade, Thomas Schmoeller, Uli Klostermann of Synopsys

Sunghoon Jang, Junghoon Ser, Insung Kim, Young-Chang Kim, Sooryong Lee of Samsung

Eric Hendrickx, Gian Lorusso of imec.


  1. [1] J.Cobb, et al., "Investigation of EUV tapeout flow issues, requirements and options for volume manufacturing," Proc. of SPIE Advanced Lithography Vol. 7969-26, 2011.

  2. [2] J. Cobb, et al., "Flare compensation in EUV lithography," Proc. of the EUV Symposium, Antwerp, 2003.

  3. [3] J. Yeo, "EUVL projection on Samsung's device roadmap," presentation at Sematech EUV Symposium, 2009.

  4. [4] I. Kim et al., "Flare mitigation strategies in extreme ultraviolet lithography," Microelectronic Eng. Vol. 85, Issues 5-6, May-June (2008).

  5. [5] E. Van Setten, et al., "EUV mask stack optimization for enhanced imaging performance," Proc. of SPIE BACUS, vol. 7823, 2010.

  6. [6] G. F. Lorusso, et al., "Extreme ultraviolet lithography at IMEC: Shadowing compensation and flare mitigation strategy," Vac. Sci. Technol. B 25, 2127 (2007).

  7. [7] M. Shiraishi, et al., "EUV mask stack optimization for enhanced imaging performance," Presentation at MNC, 2010.

  8. [8] J. Burns, et al., "EUV buried defect avoidance," Proc. of SPIE BACUS, vol. 7823, 2010.

  9. [9] S. Jang, et al., "Requirements and results of a full-field EUV OPC flow," Proc. of SPIE Vol. 7271-46, 2009.

  10. [10] L. Zavyalova, et al., "OPC flare and optical modeling requirements for EUV," presentation at 2008 International workshop of EUV Lithography, May, 2008.

  11. [11] International Technology Roadmap for Semiconductors (ITRS) roadmap for EUV masks;

Contact author:

Kevin Lucas, Corporate Applications Engineer, may be reached at Synopsys, Inc., 1301 S. Mopac Expressway, Austin, TX, 78746; ph.: 512-372-7584; email

Solid State Technology | Volume 54 | Issue 8 | August/September 2011

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