Technology trends to watch
Over the next ten years, we will see increased use of high-k metal gates, and a fairly quick move to fully depleted device architectures, such as the FinFET. This will be followed by some kind of strain engineering, likely in the channel because external stressors will not be effective at smaller dimensions. Later, we'll enter into an age of more revolutionary devices, such as tunnel FETs. These are the predictions made by An Steegen, imec's senior vice president of process technology development, speaking at The ConFab 2011 in May.
"The logic device roadmap is still very much driven by the continuation of Moore's Law," she said. "It's simple ??? shrink the area 50%, improve your performance 25% at scaled Vdd, reduce the power by about 20% and do that every two to three years."
Up until the 90nm technology node, Steegen said the industry could meet the ppa requirements (power, performance and area) just with lithography. At the 65 nm node, however, two problems started to occur. The first one was an increased gate leakage due to tunneling current that became dominant in the gate stack. The other one was the device off current. "What happened at that point is that litho along was not enough anymore to give the required ppa for the nodes to come. We had to start looking into new materials and device architectures. That's basically when we entered the era of materials-enabled scaling in the device roadmaps," Steegen said.
Noting that both gate-first and gate-last high-k metal gate integration schemes have been successfully used in manufacturing (the key difference between the two is the thermal budget that the gate stack sees), Steegen said there are still some challenges to be overcome in high-k scaling. One of them is the PFET work function at EOT thicknesses below 10??. "Fermi level pinning causes the PFET work function to roll off," said said. "The other one is the reliability of that gate stack below 10??, which also clearly poses some challenges."
To improve the off-current of the device, Steegen said the trend is to move to ultra-thin body, fully depleted devices, such as the FinFET introduced by Intel earlier this year. "Here there are many integration flavors that you can use to implement the fully-depleted device. There is the FinFET and ultra-thin SOI, or an implant-free quantum well device," Steegen said. She believes it is too early to pinpoint which approach will be the most widely adopted but said imec was benchmarking all three. "We're able to trade off the pros and cons for each of these integration schemes," she said.
Beyond fully depleted devices with high-k metal gates, Steegen said the industry will have to change how it employs stressors (i.e., tensile compressive nitride liners at the epi source/drain) to improve device performance. "When you start scaling the dimensions to 14nm and below, they become less and less effective," she said. "One way of improving the device performance is by engineering the channel mobility." The way to do that is by introducing new materials, such as germanium and III-Vs, in the channel. Steegen said imec has already been working for a long time on germanium devices, so that work is well established at this point. "A lot of focus these days is on the III-V devices. We're very proud at imec that we could demonstrate the first transistor built on a III-V material, grown on a 300mm silicon substrate," she said. However, there's still a lot of work to do on these III-V transistors. "Clearly, the substrate defects are a big issue. The other one is the passivation of the III-V materials," Steegen said.
Looking even further out, Steegen said there were many flavors of exploratory devices that could replace the MOSFET. "One of them that's really getting a lot of attention right now and is being studied quite a bit is the tunnel FET," she said. TunnelFETs use band-to-band tunneling in a gate-controlled heterojunction type of device to be able to reduce the subthreshold voltage to below 60mV/decade. "That's a pretty unique device and the way you do that is just by filtering your energy through that gate voltage and allow tunneling in the on-state of the device," Steegen said. "The key issue of this device is the on current. We can't get enough drive into these devices. We need to improve the tunnel efficiency of the source of the device by implementing new materials. It's pretty much a given at this point that a silicon-based heterojunction device is not going to work so we have to again adopt new materials, like germanium and III-V, to build this device and improve the tunneling efficiency. It's going to have to be seen if the on-current of this device can meet industry requirements," Steegen said.