Issue



Scan diagnostic analysis assists SoC fab debug/process monitoring


07/12/2011







Executive Overview


For many years semiconductor manufacturers have successfully ramped and improved yield using yield management systems (YMS) and physical failure analysis. However, with new and subtle defect types introduced at modern production nodes, and ever increasing demands for product quality and profitability, additional tools are required. A new yield analysis methodology using scan diagnosis analysis is used to improve process debug and yield monitoring. The motivation for applying diagnosis analysis is driven by scenarios in which true silicon performance may not exactly match simulation across PVT corners or where systematic defects are design-driven. In such cases, wafer-level bin maps provide limited resolution [1] for scan signatures, and trends in data may not be visible with raw pin/cycle/fail data from the automated test equipment (ATE).


Steve Palosh, Freescale Semiconductor, Austin, TX USA; Geir Eide, Mentor Graphics Corp., Wilsonville, OR USA


Freescale Semiconductor has applied a new methodology that improves process debug and yield monitoring throughout the life of its semiconductor products. Scan diagnosis analysis (also known as diagnosis-driven yield analysis) combines a more detailed diagnosis of larger volumes of failing devices with statistical analysis techniques that help separate devices failing from random and systematic defects. Diagnosis analysis can complement class probe correlation work or be used as a way to focus traditional YMS data mining on material that was processed in a specific way.


Diagnosis analysis and memory bitmapping


Memory bitmapping software has traditionally been used to classify spatial patterns, such as single bit, cluster, row, column, and row/column cross, etc., of failures. The array-like structure makes mapping of memory fails to a fault location a relatively simple computational process that is based on a detailed logical mapping of the physical memory structure.


Diagnosis analysis extends this type of analysis to yield limiters that manifest only in logic failures. Any tool that can reveal spatial patterns within the physical layout is of particular interest to the yield or failure analyst. Memory bitmapping and diagnosis analysis can each provide a high level of granularity in terms of physical localization and electrical defect classification.


Both methodologies require logging of additional fail bits from ATE at a predetermined quantity and sample rate that is likely to change depending on the maturity level of the product [2].


Compared to memory bitmapping, obtaining similar information from scan failures is a computationally intensive task that can be completed in hours to days depending on data volume and computing capability. This is because logic structures have complex functional behavior and a complex physical layout. Both physical layout and functional behavior must be considered when computing the suspected defect locations on the die.


The result of this additional computing effort is a rich set of electrical defect classifications such as stuck-at, open, bridging, and slow-to-rise, etc.


Scan logic may be considered by the yield engineer or failure analyst as a complex set of product specific test structures. Because library cells are placed in various orientations and locations with unique routing paths, they are a great complement to the uniform structure and interconnection of memory cells.


Diagnosis analysis for process debug


The case we describe here involved a new product that was being introduced simultaneously with a new fab process technology [3]. At unit probe, the yield loss was dominated by a higher than normal occurrence of scan chain bin fails near the edge of the wafer. A high occurrence of stuck-at scan fails followed closely on the bin Pareto.


Conventional methodologies for yield analysis involve trying to correlate bin map signatures with data collected from scribe grid process controls (SGPC) test structures, fab tools, and other factory monitors. In this case, these methods were not able to converge on the systematic mechanism behind these logic fails.


We performed scan diagnosis on the stuck-at pattern fail data. Our working theory was that whatever defect mechanisms were damaging the scan chains would also be damaging the functional logic. About 12% of all failing die reported a strong diagnosis callout that pointed to the clock input of many different instances of a specific library cell [3]. A design cell usage report showed us that this cell type was also the most common cell in the scan chain structures and the SoC's logic, which means that this cell was most likely to be identified as a suspect by diagnosis. Therefore, we could not conclude that there was anything wrong with this library element.


In parallel with this effort, some die with failing scan chains were submitted to failure analysis (FA) for detailed electrical and physical analysis. This process can take many weeks because of lead times associated with assembly/packaging as well as scheduling of failure analysts and specialized equipment.


In the FA lab, a chain test pattern was used to stimulate the device while a time-resolved emission (TRE) scope was used to search through the scan chain to look for abnormal light emissions. TRE scope waveforms showed abnormal light emissions on exactly the same clock input pin at several instances of that same library cell. A highly resistive via was measured through atomic force probing (AFP), and energy filtered transmission electron microscopy (EFTEM) cross-sections revealed an oxygen rich interfacial layer (Fig. 1).










Figure 1. Cell clock input with resistive via [3].

Once we were able to correlate a diagnosis callout to physical FA, it was possible to analyze a wide volume of material by looking for the particular scan diagnosis signature. This analysis included die from another product that used the same cell library and process technology.


The value of the correlation was demonstrated almost immediately. A task force of yield, process, and FA specialists was formed to investigate the source of this systematic failure mechanism.










Figure 2. FA site locations (dark) near edge of SOG area [3].

The sites found by FA (across five die) were always located near the edge of the sea-of-gates (SOG) logic area as shown in Fig. 2. Because of this fact, the team wanted to answer the question "Do resistive vias only occur on the edge of the SOG area?" Based on the five FA samples, the hard evidence observed would suggest the answer to be "yes". However, a data set of five samples is not statistically significant enough to answer the question confidently.


Performing physical FA on a significant number of die was impractical due to long lead times. A mistake in this judgment might have driven our team down the wrong path with process experiments that would take many weeks to complete. Thus, to answer the question, analysis of "layout-aware" [4] scan diagnosis results from a larger number of failing devices was performed. All callouts pointing to the same cell type and pin identified in the initial five samples were plotted and stacked against a top-view of the die's physical layout. The diagnosis analysis showed that the failure mechanism appeared to happen in all regions of the SOG area and not just near the edge. From this, the team concluded that resistive vias did not only occur on the edge of the SOG area and proceeded with the execution of several process experiments.


Software-based simulation data is never as compelling to a process team as hard physical FA. For this reason, a set of FA samples with callouts in the center of the SOG area were submitted for analysis. Many weeks later, while process experiments were underway, the FA findings confirmed the exact same via problem that was originally correlated to the cell/pin diagnosis callout.


The value of diagnosis analysis in this case example was that it offered a statistically significant alternative to performing an impractical quantity of FA. Although physical FA is often required as conclusive proof, diagnosis analysis can be used to understand the scope of the problem by classifying and localizing the defects [5]. Getting the FA picture faster and knowing where to find it is very important because of the long lead times associated with process experimentation and investigative FA.


Scan diagnosis for process monitoring


Another useful application for scan diagnosis in the yield management process involves monitoring diagnosis signatures and trends associated with split-lot experiments. One of the process experiments that we used, which was designed to modulate the resistive via mechanism, also involved varying the trench depth parameter targets associated with the resistive via. In this experiment, a split lot was analyzed that included sets of wafers processed with three specific trench depth targets. Each successive increase to the trench depth resulted in a significant yield improvement.










Figure 3. Effect of deeper trench on wafer stack and cell callout Pareto.

The experiment results suggested that increasing the trench depth improves the cluster of failures that seem to originate from the seven o'clock position on the wafer. The wafer stack for each trench depth is shown in the top of Fig. 3.As shown at the bottom of Fig. 3, the top 50 most commonly used library cells in the SoC design were plotted against the percentage of failing die on which it was called out as a suspect by the diagnosis analysis results.


This plot can be used to understand the response to process variation on a cell-by-cell basis. In this case, the plot demonstrates that there is no specific library cell sensitivity that is modulated by trench depth. This allows for a tighter focus on the problem at hand.










Figure 4. Physical heatmap Tessent YieldInsight diagnosis analysis software at each trench depth target.

One of the advantages of diagnosis analysis is the ability to visualize many kinds of signatures. For example, we generated a stacked physical heat map showing the diagnosed location of each defect for all failing die to help us understand the spatial signature of the scan fallout. Figure 4 shows this for each of the three trench depth targets.


The physical heat map is a stack of multiple die that is divided into a 200 x 200 pixel grid. Circuit elements called out by scan diagnosis are plotted in terms of their physical position in the grid. For a given square, one or more circuit elements may be present inside of a square for a given die. The color in the heat map indicates the number of die with callouts within the same square.


In this case, the overall fallout was reduced significantly at 455nm. In Fig. 4, this can be seen as an overall reduction of pixels illuminated across the die. While this major systematic was improved with the process change, a smaller systematic was increasingly visible in the lower right area of the die (indicated by the circled orange-red regions in Fig. 4). This meant that multiple die were failing in this critical location or "hot-spot."


This secondary systematic is not visible using the traditional wafer stack map shown in Fig. 3. The die level heat map based on diagnosis results offers the analyst a way to understand the limitations of the process change. It also offers an initial data point to begin analyzing potential layout sensitivities to process.


Analysis of process variations can be improved by being able to understand spatial relationships. Although fail bins have always provided spatial patterns on wafer stacks, scan diagnosis coupled with specialized visualization and analysis techniques provides the much needed sub-die resolution to reveal what were once hidden systematic issues.


Diagnosis analysis enables targeted physical FA based on a die stack or additional data analysis of class or unit probe data. Previously hidden spatial patterns can be revealed through selection or filtering of data based on various genres of information such as nets, cells, via macros, or defect classification.


Conclusion


Diagnosis analysis can provide a rich set of actionable data to the yield analyst. This includes additional yet similar benefits to what has traditionally been done with memory bitmap technology.


This article shows how we were able to leverage diagnosis analysis in a wafer fab environment. Conventional yield analysis techniques can be complemented or even directed by the findings that can be extracted from this data. Fabs that set up volume diagnosis flows early in the NPI phase will continue to benefit through the entire product life cycle.


Acknowledgments


Tessent and YieldInsight are registered trademarks of Mentor Graphics.


References


1. D. Appello, "Using Multiple Data Domains and Volume Diagnosis to Isolate Systematic Yield Detractors," International Test Conf. 2009.


2. C. Schuermyer "Optimizing the Manufacturing Test Program, Data Collection, and Diagnosis for Yield Analysis," EETimes Online, Sept. 2010.


3. D. Carder, S. Palosh, R. Raina, "High-Volume Scan Analysis: Practical Challenges and Applications for Industrial IC Development," International Test Conf. 2010.


4. M. Keim, N. Tamarapalli, H. Tang, M. Sharma, J. Rajski, C. Schuermyer, B. Benware, "A Rapid Yield Learning Flow Based on Production Integrated Layout-Aware Diagnosis," International Test Conf. 2006.


5. Yi-Jung Chang, et al., "Experiences with Layout-Aware Diagnosis ??? A Case Study," Electronic Device Failure Analysis, May 2010.


Biographies


Steve Palosh earned a BS in electrical engineering from DeVry U. and an MBA from the U. of Phoenix. He is a senior member of the technical staff in the Microcontroller Solutions Group at Freescale Semiconductor, 6501 West William Cannon Drive, Austin, TX 78735 USA; ph.: 512-895-2000; e-mail: steve.palosh@freescale.com.


Geir Eide earned a BS and MS in electrical and computer engineering from the U. of California at Santa Barbara and is a product marketing manager in the Silicon Test Solutions group at Mentor Graphics Corp., 8005 SW Boeckman Rd., Wilsonville, OR 97070 USA; ph.: 503-685-7943; e-mail: geir_eide@mentor.com.


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