Issue



Pioneering new devices and materials for future ICs


05/01/2011







Executive Overview

The computation and storage capabilities that will be expected from future ICs and systems require that we go on scaling. Because we are closing in on the physical limits of IC scaling, we have to push the technology to the extreme. That is why we are developing new transistor architectures and introducing new materials and processing techniques. Our goal is to develop processes that can be used in high-volume manufacturing of future logic and memory ICs. In our R&D into logic ICs and peripheral DRAM, we follow two tracks. One is refining established technologies for the next generation of ICs, and a second is exploring and developing the options for further generations.

Thomas Hoffmann, imec, Leuven, Belgium

The first R&D track at imec is concerned with the 22nm and 15nm technologies − for the generations of ICs that will be produced starting this year, and in 2013, respectively. We've looked, for example, at the possibilities and issues to scale high-k/metal gates, which were introduced at the 32nm node, beyond the 22nm node. Also, we've examined two competing processing options – gate-first and gate-last – looking for the best trade-off between performance and integration complexity. As a result of this research, we can give our partners recommendations on how to best set up their IC manufacturing processes.

Our main effort, however, is on technology for ICs that will be produced in 2015 and later, i.e., ICs with smallest dimensions of less than 15nm.

New transistor architectures

From the 15nm node on, it is expected that we will need a new transistor architecture to maintain device functionality and control as the dimensions shrink further. To accomplish this, fully depleted device concepts (like multi-gate devices or fully-depleted SOI devices) are envisioned. Among those, One of the most likely candidates is the FinFET architecture, on which we have been working since 2004. The distinguishing characteristic of these devices is that the conducting channel is formed by a thin silicon fin on which the gate wraps around. We are currently scaling our SRAM-cell FinFET demonstrator, first to the 15nm technology, but already with an eye on 11nm. We're also working on some of the remaining challenges, some of which have to do with the 3D structure of FinFETs, e.g., etching the 3D fin or integrating stressors.

We're also doing a lot of exploratory research to assess the viability of more disruptive, less established technologies. Examples are the use of germanium or III-V channel materials, the use of TunnelFET devices, and the introduction of graphene and nanowires in IC processing.

Further developing the FinFET concept, we're looking to boost its performance by incorporating new materials. We've started work on a germanium-based high-mobility FinFET, which we'll further develop this year. And we're also planning to incorporate III-V materials in the FinFET channels.

One of the architectures that might supersede FinFETs is TunnelFETs. These are based on semiconducting nanowires and allow an optimal electrostatic control of the transistor channel. TunnelFETs are switched on by exploiting quantum-mechanical band-to-band tunneling. They promise to work with a supply voltage below 0.5V, thanks to much steeper turn-on characteristics than is possible with even FinFETs. We also know that they will benefit from integrating germanium and III/V materials. So all our current experience with those materials can be leveraged and carried over to TunnelFETs.

A lot of the work we do is limited by the possibilities of patterning. If EUV lithography continues to make progress and evolves towards what is theoretically possible, then patterning down to 7nm devices could become a reality. But at that scale, the complexity of designing and processing ICs will be such that for some applications, another road might be followed: i.e., 3D stacking of ICs. To prepare for that possibility, we're also looking into the combination of FinFET ICs and 3D stacking with through-silicon vias. Because we have the processing capabilities for FinFETs and for 3D stacking, we can make working prototypes. These allow our partners to make assessments of the costs of such ICs, and the systems that can be built with them. This, in its turn, gives us valuable feedback on the challenges that we still have to solve.

Biography

Thomas Hoffmann received his PhD degree from Lille U. (France) and is the director of the FEOL Logic Devices Program at imec, Kapeldreef 75, B-3000 (Belgium); ph.: (+32) 16281099; email thomash@imec.be.

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