Issue



Nano-porous dielectrics and copper barriers for 28nm and below


05/01/2011







Executive Overview

Nano-porous low-k films are the standard interlayer dielectrics (ILD) at 45nm, but they are relatively fragile. Improvements in the low-k films and their associated copper barrier dielectrics have been developed to optimize mechanical strength, damage resistance, and electrical performance of the dielectric stack for use in production at the 28nm node and below. New chemistries have yielded controlled polymerization during ILD deposition and, combined with optimized UV curing, films with smaller pores with tighter size distribution and increased mechanical strength – all without sacrificing k. Engineering of the barrier-to-copper interface has eased integration of the new nano-porous low-k films and has yielded enhanced electrical performance and reliability of the resulting interconnect circuit.

Harry Whitesell, Eric Hollar, Kang Sub Yim, Li-Qun Xia, Thomas Nowak, Applied Materials, Santa Clara, CA USA

As devices continue to scale down, device speed – characterized by RC delay - is significantly affected by the dielectric constant (k) of the insulating materials sandwiched between the copper interconnects. To achieve desired electrical performance, the effective k value (keffective) of the ILD combined with any associated barrier films must scale correspondingly. Thus, we have seen a steady progression of dielectric materials in recent years as conventional ILDs gave way to low-k materials (k<3.9) for 65nm production, and are now being replaced by nano-porous low-k films (k<2.7) for 32nm and below. Since keffective is a measure of the combined effects of the ILD and the copper barrier, care must be taken not to offset k reductions in either layer by potential increases in the other.

In addition to the change in materials, ILD and copper barrier film thicknesses have been decreasing as geometries have continued to shrink. This has been necessary to reduce their encroachment on the metal interconnect volume vital for current flow. Since the dielectric constant of the copper barrier is typically much higher than that of the ILD, there is a need to minimize the thickness of the copper barrier in particular to minimize its impact on keffective of the dielectric stack. As the low-k dielectric becomes more porous, the copper barriers are increasingly crucial to back-end-of-line device reliability. This strongly impacts design of the processing steps needed to integrate the copper barriers since these films must protect the ILD and ensure reliable long-term operation of the device while minimizing their thickness. Reliability metrics that need to be met include electromigration (EM) performance, time-dependent dielectric breakdown (TDDB), and line-to-line leakage.

Here we highlight several advances in semiconductor fabrication at 28nm and below that address the fundamental issues with resistance to chemical attack and mechanical strength of the nano-porous low-k material, the effectiveness of the copper barrier, and the resulting reliability of the interconnect structure.

Scaling to 28nm

The year 2011 will see leading-edge semiconductor manufacturers starting to implement 28nm in production, driven by the demand for chips to feed the burgeoning markets in handheld multi-media devices. These end products are in turn driving more sophisticated process sequences and packaging methods that will require greater robustness from bulk dielectrics and copper barriers. In recent years, process and technology development have therefore been focusing increasingly on modifying the chemical composition and structure of the films to optimize their production-worthiness.

Enhancing ILD properties. Nano-porous low-k films with a dielectric constant of approximately 2.5 are the industry standard for the 45nm node. As described elsewhere [1], these films are most effectively fabricated using a two-step process. First, an organosilicon backbone is co-deposited with a labile phase that will partially define the final pore space. Second, an advanced curing step, optimally an ultraviolet (UV) cure, is applied to the film to remove the labile phase and to restructure the remaining matrix to form the final nano-porous film. This porosity helps to reduce the final dielectric constant of the film, however, it can also make the film extremely susceptible to material damage during subsequent wet and dry processing steps. At 45nm, this challenge has been successfully managed. Achieving ultra-low-k (k~2.2) film for scaling to 28nm and below, however, requires re-engineering of the ILD's composition and structure to improve its ability to withstand subsequent downstream plasma etch, photoresist ash, wet clean, and chemical-mechanical planarization (CMP).

To determine the most effective chemistry for making a robust nano-porous low-k film, comparative studies were conducted of various organosilane precursors with different carbon-based backbone structures and an organic precursor for the labile, pore-forming phase. Among the organosilane precursors the key differences included the nature of the carbon bridge, seen to largely determine resistance to integration damage, and methyl content. Comparisons of commercially available options showed that a new, proprietary precursor needed to be developed as the methyl in the existing chemicals tended to decrease the mechanical strength contributed by the carbon.

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Figure 1. Curing the bulk dielectric with UV light substantially improves its modulus, while achieving k values as low as 2.1.

Having engineered a precursor with the appropriate carbon content and bonding gave the desired chemical resistance. As with the existing generation of 45nm films, the key to achieving the desired mechanical strength (elastic modulus, E, and hardness, H) and dielectric constant was applying a UV cure to the film. This process promotes cross-linking of the dielectric backbone, creating a denser, stronger material. It also drives out the labile species, thereby lowering the k value —in this case attaining a k value as low as 2.1 (Fig. 1). Besides strength and low k value, the "re-engineered" film also exhibited desirable shrink resistance and low stress during the cure process. Its high modulus (E>6.5 GPa) gives this film the mechanical strength required to withstand packaging integration.

Improving the copper barrier. The baseline copper barrier material for 45nm production is an amorphous dielectric material composed of SiCN and possessing a k value of approximately 4.0. At 28nm, meeting the capacitance reduction requirement involves not so much a change in the bulk k value, but rather a change in film thickness. On the other hand, as the metal lines and the distance between the lines shrink further, device reliability (TDDB and EM) becomes a real concern. Various interface enhancement techniques have been adopted to address the interfacial adhesion strength and dielectric properties, while minimizing the damage to the underlying low-k materials.

Besides a native copper oxide, organic impurities from CMP cleaning are present on the exposed copper of a device wafer entering the SiCN deposition chamber. Pre-treatment must remove these, creating a clean copper surface with minimal damage to the k value of the exposed nano-porous ILD. This is accomplished by a pre-treatment sequence using multiple sub-steps of plasma-assisted reducing chemical reactions that target copper oxide removal or impurity removal. The pre-treatment process results in a clean copper surface for optimal adhesion, EM, effective line resistance, and leakage performance.

Once the copper surface is prepared, a thin initial dielectric layer is deposited. This layer must block the diffusion of copper and is critical to ensuring good electrical properties (EM and TDDB) of the device [2,3]. A thin layer of copper silicide (CuSix) is used to prevent copper diffusion. It is formed by depositing a thin layer (~30Å) of silicon-rich nitride (SRN) on the clean copper surface. The excess silicon in the SRN reacts with the surface copper to form the even thinner layer of CuSix, locking this copper to the SiN matrix and preventing further diffusion of the copper atoms. The silicon for CuSix formation derives from the SRN matrix, which self-limits the reaction to the first few atomic layers of copper.

Because SRN is electrically leaky, a subsequent nitridation step is required to convert the remaining SRN layer into a low-leakage, hermetic, high-quality SiN film. The enhanced nitride interface (ENI) scheme has several advantages over alternative approaches. ENI is conformal to ensure sufficient step-coverage, especially on surface topography at the trench corner where copper, metal barrier (Ta/TaN), intermetallic dielectric, and SiCN converge. The self-limiting nature of the CuSix reaction ensures that the ENI does not consume excessive copper, which would adversely affect sheet resistance and RC delay. Furthermore, the ENI layer is easily measured with common fab metrology tools, facilitating film monitoring essential for maintaining a production-worthy process. The ENI scheme is in production at multiple device manufacturers and is under evaluation at several others. Electrical tests using this scheme on a two-level copper damascene structure show a 2X EM improvement (Fig. 2) [4].

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Figure 2. Electrical tests for SiCN barrier show improved TDDB in a single-level copper test structure (left) and more than 100% EM improvement in a two-level copper damascene structure (right).

Besides satisfying barrier leakage and adhesion requirements, the high-quality interface nitride layer also serves as a barrier to moisture and oxygen penetration, which allows further reduction in bulk barrier low-k (BLOk) thickness based on etch requirements.

22nm and beyond

With the industry on the cusp of running 28nm devices in production, can 22nm be far behind? Some manufacturers are, in fact, preparing to launch production later this year as well, citing demand from the computer and server segments for the higher performance, improved power efficiency, and longer battery life these designs promise. As with 28nm, the extendibility to 22nm and beyond of nano-porous dielectrics and copper barrier films lies in continued refinement of chemical interactions to attain desired characteristics in each layer.

Improving low-k ILD integration. Generating smaller pores with a narrow pore size distribution, while preserving mechanical properties and low dielectric constant, are the key objectives in ultra-low-k development. Several precursors show promise, while maintaining k values ranging from 2.4 to 2.2. This work has capitalized on the compositional uniformity of the chemistry and refined delivery control by the deposition system to achieve extremely thin transition layers (75% thinner) that have lowered keffective while preserving excellent adhesion. An additional silicon precursor, introduced to increase cross linking, improved the film's mechanical strength (~ 6.5 GPa at k=2.3). Coupled with an advanced, optimized UV cure that improves shrinkage uniformity, the final result is a film that is flexible in dielectric constant range and modulus, and can be deposited in thinner layers with lower keffective.

Copper barrier development. For scaling to 22nm, a sub-10nm copper barrier is required for lower keffective while maintaining the reliability performance. In addition to conventional barrier properties, conformality becomes an important requirement to compensate for surface topography in properly sealing the copper surface. Stronger interface bonding between the BLOk and copper is required to offset the reduction in contact area as devices shrink. New disruptive concepts are being explored; initial results using a 55nm device demonstrate 100X better EM performance than state-of-the-art barriers. Further tests are underway to determine how results from the 55nm device will extrapolate to devices fabricated at 20nm and below.

Conclusion

Interconnect scaling is no longer just about lowering dielectric constant. The challenges of minimizing RC delay must be met while simultaneously meeting all packaging and other electrical performance and reliability requirements. This requires an integrated approach for the dielectric stack combining optimization of the ILD with the dielectric copper barrier. Current low-k dielectric films offer a flexible range of dielectric constants, modulus, and hardness, enabling designers to adjust the film properties to requirements at each metal level. Copper barrier solutions exist that ensure electrical and reliability performance even as device scaling continues.

References

1. S. Jain, V. Zubkov, et al., "Porous low-k dielectrics using ultraviolet curing," Solid State Technology, 48:9, pp. 43-46, 2005.

2. M. W. Lane et al., "Relationship between interfacial adhesion and electromigration in Cu metallization," J. App. Phys., 93:3, pp. 1417-1421, 2003.

3. A.S. Lee et al., "Reliability of dielectric barrier films in copper damascene applications," Mat. Res. Soc. Symp. Proc., 812, F5.10.1, 2004.

4. L.-Q. Xia et al., "Second generation copper dielectric barrier (BLOk II): k reduction and interface control to improve TDDB and EM," ECS Trans., 18:1 pp. 593-599, 2009.

Biographies

Harry Whitesell received his BS in mechanical engineering from West Virginia U. and PhD in materials engineering from Auburn U., and is Global Product Manager at Applied Materials, Inc., 3330 Scott Blvd., P.O. Box 58039, Santa Clara, CA 95054 USA; email Harry_Whitesell@amat.com.

Eric Hollar received his BS in materials science and engineering from North Carolina State U. and his PhD in materials engineering from the U. of Illinois at Urbana-Champaign. Eric is Global Product Manager at Applied Materials, Inc.

Kang Sub Yim received his PhD in chemical engineering from Stanford U. and is a Senior Member of Technical Staff at Applied Materials, Inc.

Li-Qun Xia received his BS in chemical engineering from the East China U. of Science and Technology and his PhD in chemical engineering from Cornell U. He is Senior Director of Dielectric Systems and Modules at Applied Materials, Inc.

Thomas Nowak received his BS and MS degrees in mechanical engineering from Worcester Polytechnic Institute and his PhD in mechanical engineering from the Massachusetts Institute of Technology. He is a Distinguished Member of Technical Staff at Applied Materials, Inc.

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