Packaging Roadmaps at MEPTEC
The status of semiconductor packaging roadmaps was the focus of a forum hosted late last year by MEPTEC (Microelectronics Packaging and Test Engineering Council), a trade association of semiconductor suppliers and manufacturers. MEPTEC brought together a group of experts from AMD, Altera, Amkor, ASE, Cisco, LSI, Micron, TechSearch, Unisem, Yole and other companies and organizations.
Bill Bottoms, CEO of 3MTS gave the introductory talk taking a look a collaborative roadmaps and international roadmap perspectives. From his position as chair of the ITRS (International Technology Roadmap for Semiconductors) packaging and assembly TWG (technical working group) Bill reminded attendees that ITRS is sponsored by Europe, Japan, Korea, Taiwan and the US to forecast semiconductor technology requirements 15 years out, and to forecast emerging semiconductor devices and materials 10 years out.
In addition to the ITRS, i-NEMI is the pivot point for all microelectronic packaging activities of a variety of organizations, including IMAPS, IPC, INSIC, OIDA, IEEE, CPMT and USDC. On a global basis, the other organization looking at overall semiconductor packaging solutions is JISSO, a Japanese term which reflects the total packaging solution for electronic products.
Bottoms' premise is that for the past 40 years semiconductor progress could be easily predicted. The focus was on design and fab. Semiconductor roadmap goals were all clearly focused on shrinking geometries (scaling) and increasing wafer size. However, as we enter the "deep submicron" era, things become more complicated and packaging becomes more important in delivering semiconductor yield, reliability and performance.
The answer developed to address the historical lack of package scaling to match IC scaling was to generate the packaging at the wafer level, i.e. wafer level packaging or WLP. WLP, now firmly entrenched as a packaging option, offers portable consumer products several benefits: inherently lower cost, better electrical performance, lower power requirements, and smaller size.
Another important trend in packaging is the incorporation of multiple die into a single package or what has become known as System in Package (SiP), or MCM (to those of us that have been around awhile).
Moving forward, Bottoms predicts, as many of us do, that the 3rd dimension will be the key enabler in maintaining the "price elastic growth of the electronics industry." While 3D presents many challenges they all appear to have reasonable solutions. 3D will appear first through silicon interposers with through wafer connections and then through chips fabricated with internal TSV for through wafer connections.
Bill updated attendees with where the packaging roadmap would be increasing and expanding coverage in 2011. Bottoms concludes that the pace of change in packaging technology has never been greater and roadmaps are critical to continuation of this rate of progress.
Bryan Black of AMD looked at why 3D is required if semiconductor technology is to continue to move ahead. In standard fashion Black defines 3D technology in two varieties: TSV in active devices and TSV on interposers.
From a systems standpoint Black proposes the interesting perspective that performance density drives new form factors, new form factors discover new usage models and without new form factors the industry would stagnate.
The latest edition of the ITRS notes that the expansion of 3D architectures for packaging poses unique challenges that are not encountered in conventional 2D packaging. These include: Thinning wafers and die, and the handling of these thinned wafer and die; Thermal management when several layers of semiconductor devices are stacked; Power delivery and the maintenance of power integrity as the operating voltages are dropped to near the threshold voltage; and testing for 3D structures when test access is a challenge.