The road ahead for SiPs


Executive Overview

Over the years, systems-in-package (SiP) have gained huge popularity because of the many advantages they offer – including the ability to integrate diverse chip technologies such as micro electro-mechanical systems (MEMS) and passives; as well as improved time to market, size, and cost. In this article we discuss the challenges in design, materials and processes brought about by new SiP applications and chip technologies. We will also address some of the discontinuities in SiP design, materials and processes and possible paths forward.

Darvin Edwards, Masood Murtuza, Texas Instruments, Dallas, TX USA

SiP growth is fueled by the fast-changing personal electronics market requiring smaller sizes, high performance and a platform capable of adapting quickly to changing chip technologies. Examples of current SiPs include radio frequency (RF) modules, which enjoy wide use in cell phones, and direct current (DC) power conditioning blocks. The 2009 ITRS has described the future SiP growth model under the title "more than Moore" [1]. In this vision, adding functionality with SiP technology leapfrogs traditional scaling approaches to accelerate time to market for tomorrow's products (Fig. 1).

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Figure 1. System in package integration leapfrogs traditional scaling approaches, providing "More than Moore" functionality. SOURCE: Semiconductor Industry Association. The International Technology Roadmap for Semiconductors, 2009 Edition. SEMATECH, Austin, TX, 2009.

The success or failure of SIP designs depends upon the design, process, and test teams – wherever they are located - working together to ensure all components integrate well. These teams extend beyond an individual company to incorporate all the critical suppliers of the SiP. Often, establishing the team and inter-company relationships is the most difficult barrier to SiP integration. As SiPs become more complex, improved inter-company relationships will be increasingly important to successful design and fabrication. The following sections discuss specific challenges and technology choices team members must address.

Overcoming design complexities. As SiPs use devices from different sources, design data porting from different sources to the SiP design has become increasingly complex. This means custom design features are required, as well as a design process that must recognize the interactions between all components. For example, an optimum pad placement plan for a device slated for the usual single chip package may not translate to the SiP environment. Therefore a co-design approach to chip layout will create the best trade-offs between I/O locations, system performance, package complexity, and even cost. The co-design usually entails coordination between cross functional teams from all the component suppliers to ensure successful design. These tight inter-company interactions reduce surprises which may lead to product delays. When families of SiP solutions are developed, design decisions from the driver product can be used to produce design templates to speed future development.

An increasing need for thermal management. Chips with different maximum operating temperatures are often packaged together, and ever-increasing levels of integration drive higher thermal densities, which must be well managed in SiPs. The thermal design must optimize the system for the "weakest link" device, or the device with the lowest maximum operating temperature. Integration of non-Si technologies such as gallium nitride (GaN) or silicon carbide (SiC) into SiPs will allow much higher operating temperatures than traditional Si technologies. This will require not only partitioned heat sinking, but thermal isolation between devices operating at different temperatures. Integration of materials with different maximum temperature ranges within a package may also be needed.

Interconnection advancements. Through-silicon via (TSV) and other fine pitch interconnections such as copper (Cu) pillars are more sensitive to substrate planarity and warpage since the amount of solder that provides warpage tolerance during reflow is less. These interconnects require substrates that are dimensionally stable over a wide temperature range in order to make the solder joints. Current packaging materials and processes are essentially scaled versions of coarser pitch solder bump flip chip technologies. Improvement is ongoing to control warpage and surface roughness to enable finer pitch interconnects, but more advances are needed.

The industry is considering newer, temperature stable substrate materials, glasses, and other materials. Careful evaluation of the solder joint reliability is also needed because the small Cu tips in TSV and Cu pillar technologies are prone to completely dissolve and to produce metallurgies that are different from the well known Cu-solder systems. Similarly, non-solder interconnect systems, including conductive pastes and nano-metals, should be studied to enable next-generation interconnect schemes beyond solder-to-metal approaches. New challenges must be addressed to meet the requirements of emerging applications that can place special requirements on interconnections. For example, in medical applications for analysis of blood, etc., the sensor must be disposable; this requires temporary high density interconnections from sensor or MEMS to the SiP.

Reliability considerations. The development of portable sensors for temperature, humidity, chemical and biological species and ability to process and transmit data from local sites have opened up new applications for SiP "always-on" systems. These will drive the development of new high-temperature, moisture-resistant and chemical-resistant materials. Outdoor applications such as electronics for automobiles, base stations, to-the-house fiber optic connections, and solar panels have components exposed to the elements and need to be resistant to rain, atmospheric chemicals, and long term sunlight exposure. Additionally, low maintenance infrastructure applications must be able to operate reliability for extended periods such as 20-25 years. These harsh environment requirements are driving the need to better understand the link between failure modes accelerated by traditional package reliability tests and field failure modes.

Future directions

Optical chip-to-chip interconnects within a SiP are likely to gain prominence in the coming years, but integration of wave guides and coupling of wave guides to ICs are major challenges. Multiple research organizations are investigating solutions to switch optical signals within a package, distributing these signals through a 3D die stack, as well as from package to package. Glass substrates have emerged as a strong candidate for such applications [2].

Additionally, embedding passives and actives in the substrate enables even higher integration density in SiPs. With embedding, the passives or active chips are built into the substrate during the manufacturing process. As these chips become more complex, finer pitch interconnections for the substrate will be needed. The business model will increasingly involve engaging the substrate supplier to integrate multiple components of the final packaged product; hence, the substrate supplier will increasingly become a key participant in the overall design team for product success.


In summary, SiP solutions can enable even more novel electronic products with faster time to market than would be possible with traditional scaling. Proper up-front evaluation of SiP designs, having a tool box of enabling technologies, and coordination between all involved parties will be a critical requirement Many are working toward overcoming these challenges.


1. ITRS 2009. Executive Summary section, p. 10, and Assembly and Packaging section, pp. 21-22.

2. H. Schröder, L. Brusberg, R. Erxleben, I. Ndip, M. Töpper, N. F. Nissen, H. Reichl, "GlassPack – A 3D Glass Based Interposer Concept for SiP with Integrated Optical Interconnects," ECTC Conf. Proc., 2010.


Darvin Edwards received his BS in physics from Arizona State U. and is a TI Fellow and Manager of SC Package Modeling and Simulation at Texas Instruments, 13020 TI Blvd., MS 3621, Dallas, TX 75243 USA; ph.: 214-567-3569; email:

Masood Murtuza received his BTech in mechanical engineering from Indian Institute of Technology, Madras, India and an MSc from U. College, U. of London, UK, and is a TI Fellow in SC Packaging at Texas Instruments, Stafford, TX USA.

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