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SICAS: Utilization slips, but still high

Utilization rates slipped in 3Q10 for the first time in six quarters as actual wafer starts inched up slightly less than capacity, according to the latest data from SICAS. But utilizations are still exceedingly high: roughly 95% for both ICs and total semiconductors (vs. ~96% in 2Q10 and ~87% a year ago.

Total semiconductor manufacturing capacity was up 1% in 3Q10 to 2146.9K wafer starts per week (WSPW), about the same pace as in 2Q10. Actual wafer starts/week rose just 0.4% to 2039.3K WSPW, down from 3%-4% over the past several quarters. For ICs only, capacity rose 0.8% Q/Q to 1953.0K WSPW, while actual wafer starts crept up 0.3% to 1853K WSPW. Capacity is now back to 1Q09 levels for total semiconductors and total ICs, but those are still well below the previous capacity peaks from 3Q08: -11.5% for total semis and -12% for ICs, respectively.

Foundries, meanwhile, added another 4.4% capacity in 3Q10 to 424.9K WSPW, and increased wafer starts by 4.9% to 422.0K WSPW, pushing foundries' capacity utilization to 99.3%, up from 98.8% in 2Q and just 91.9% a year ago. 


A survey of 118 senior semiconductor execs by KPMG and the SIA finds that 78% expect the industry to grow >5% in 2011 (vs. 87% in 2009), 39% of respondents see ≥10% sales growth in the next fiscal year (vs. 54% in 2009), and 37% see >5% profit growth in 2011, about half as many as a year ago. Nevertheless, execs remain cautious: 53% anticipate a cyclical peak in the next 12 months.

SEMATECH, the SIA, and SRC have established a new 3D Enablement program targeting standards in inspection, metrology, microbumping, bonding, and thin wafer and die handling. SEMI International is forming a standards committee to evaluate and create specifications and practices for 3D stacked ICs, e.g. bonded wafers, inspection/metrology, and thin wafer handling. And the Global Semiconductor Alliance is creating a 3D IC initiative and seeking to work with other organizations on a broadly accessible 3D IC ecosystem.

MEMC says a court ruling means its SOI wafer processes don't infringe Soitec patents—but that Soitec could be in violation of MEMC's patents.

The proposed merger between test vendors Verigy and LTX-Credence has a new wrinkle: Advantest has submitted an unsolicited ~$700M bid for Verigy, which said it favors the LTXC transaction but will engage Advantest as a possible "superior transaction."

ISMI has launched a program to specifically address issues for "mature fabs," e.g., cost and productivity pressures, equipment lifecycle management, safety procedures, and logistics.

GlobalFoundries and SVTC have signed a joint technology development agreement to accelerate high-volume MEMS manufacturing by 3Q11, with a dedicated line in GF's Fab 3E in Singapore.

Carl Zeiss SMS and Synopsys will collaborate on in-die registration metrology for photomask manufacturing, dubbed "PROVE," for ≤32nm technology nodes.

Rudolph Technologies is partnering with an unnamed major OSAT company to provide its inspection and metrology capability in the development of stacked packaging processes using silicon interposer technology (aka "2.5D IC").

The global smartphone IC market is expected to register a strong 20% CAGR through 2010-2014, according to IC Insights.


Intel has pledged to invest $6B-$8B in a new development fab ("D1X") in Hillsboro, OR and 22nm upgrades to four other fabs (D1C and D1D in OR, and fabs 12 and 32 in AZ). With a proposed R&D startup in 2013, D1X appears likely to focus beyond the 16nm node, which means it'll involve EUV lithography work and eventually 450mm wafers.

ISMI will relocate its headquarters and operations to CNSE's Albany NanoTech Complex beginning in January.

Micron has obtained $1.5M in city and state funding to expand its chip operations in Manassas, VA.

Tegal has launched a new member of its ProNova family of high-density inductively coupled plasma (ICP) reactors, targeting 200mm MEMS and 3D IC applications.

ON Semiconductor is installing an additional $15.7M worth of production equipment in its 200mm facility in Pocatello, ID,.

Kulicke & Soffa says its new IConnPS ProCu wire bonder offers a new level of capability for packaging lines transitioning from gold to copper wire bonding.


A mid-Dec. power plant outage shut down some of Toshiba's NAND flash output for roughly two days; the company's estimates of a resulting -20% shortfall in NAND flash output through February, though, are seen by industry watchers as conservatively high, with likely little long-term impact to global supplies or pricing.

DaiNippon Screen and Sokudo say they have achieved a record dual-track productivity (>6000 wafers/day in volume for standalone systems), and are eyeing a >450wph demo sometime in late 2011.

Mattson has received a repeat order for its Alpine etch system for a leading-edge 300mm packaging facility in Asia.

Ultratech has opened an advanced manufacturing facility in Singapore, with plans to invest $125M over the next few years.

Dainippon Screen is said to be readying a new wafer pattern inspection system for "green" devices.

Fujitsu Semiconductor Ltd. will transfer its flip chip mounting technology to a Chinese group affiliate for system chip assembly.

Sanyo Semiconductor reportedly plans a 40% ramp of production capacity for discrete chips at lines in China, Taiwan, and Thailand.

Advantest is touting two new systems: the E3630 SEM-based CD measurement system for next-gen photomasks and patterned media, and the T2000 system to massively parallel test CMOS image sensor devices.


Altatech has unveiled its new EyeEdge wafer-edge inspection system to detect and image ~2µm defects, with 100wph throughput.

TEL and Tanaka Kikinzoku Kogyo have developed a successful recycling process for ruthenium precursors.

SUSS MicroTec and Fraunhofer IST have launched SELECT, a technology for bond aligners and mask aligners that selectively activates parts of wafer surfaces through plasma.

A 42-month ENIAC program, "LAST POWER," aims to develop European technology for the complete production chain for wide band gap semiconductors, devices built with SiC and GaN on silicon wafers.

Alchimer says its electrografting technology has been validated by scientists at RTI International (RTI) for depositing "insulator, barrier and seedlayer into high aspect ratio TSVs."

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