A reality check with Intel


Click to EnlargePete Singer

The 55th International Electron Devices Meeting (IEDM) will be held next month, from December 7-9, at the Hilton Baltimore. The conference is well known as the place where semiconductor manufacturers officially unveil the latest technology advances and some of the emerging, research-level types of devices are reported for the first time. This year, the hot emerging technology will be graphene nanoelectronics: researchers will be talking about how to integrate graphene into field-effect transistors, interconnects and other IC applications; graphene-based heterojunction devices that exhibit full quantum transport; spin transport valves that may lead to spintronics-based graphene devices; and nano-electro-mechanical devices.

While it's very easy to get excited about these and other promising advances that could potentially transform the semiconductor and related industries, a little reality check might be in order. For me, that came through an interview with Intel's Mark Bohr, who described the company's CPU and SoC technologies that will be presented at this year's IEDM. Bohr is an Intel senior fellow and director of the technology and manufacturing group.

What's interesting to me here is that Intel is not talking much about new process technologies, but rather the evolution of SoC. Intel first unveiled an SoC chip with the 45nm (internally a "dot" version, the p1266.8.). With the 32nm version and moving forward, Bohr said there are enough significant differences between the SoC and the CPU version to give its own number to the SoC version. 1268 is the CPU version, the 1269 is the SoC version of 32nm.

Intel's 32nm, and most likely the 28nm, transistors for both CPUs and SoCs use high-k metal gates (HKMG), strained silicon, and employ immersion lithography. What's interesting to me is what they do not employ—no tri-gate designs and no III-Vs in the channel region, for example.

"Those types of more exotic solutions are not needed at this generation, although we are continuing to explore them in our research group for future generations," Bohr said. "Keep in mind, though, that high-k metal gate is still relatively new. Intel is the only company shipping high-k metal gate, and we did that successfully at 45—and this is the second generation, so there's still more to squeeze out of high-k metal gate technology."

Ditto for next-generation lithography solutions. "We think immersion lithography will be with us for a few more generations," Bohr notes. "We'd like to have EUV, but it looks like it just won't be ready in time for 22nm, and maybe not even for 15nm. In the meantime, we'll have to make do with immersion lithography, and we think a greater use of double patterning techniques will be the way to do that—to extend immersion before EUV is ready. Bohr adds, "The nanoimprinting idea has been out there, but I'm skeptical about whether it is going to be very viable for manufacturing applications."

Instead of the exotic, Intel is instead emphasizing SoC products, which tend to require a broader range of device types. "In addition to the normal logic transistors, you need to include analog device elements, such as inductors and precision capacitors," Bohr explains. "You also need to provide a wider range of transistor types, from the high performance transistors used on CPUs to some very low leakage, low power transistors needed where long battery life is important. Also, system-on-a-chip products need to support a wider range of legacy I/O voltages; thus, we have to add some special transistors that are tolerant to higher voltage conditions."

SoC chip also have different interconnect requirements. "For the metal interconnect system for CPUs, those interconnects tend to be optimized for higher performance, meaning some of the upper layers tend to use thicker and wider copper lines than the lower layers—that's to provide higher speed interconnects across the surface of the chip," says Bohr. "But for SoC products that run on lower frequencies, they don't need the same higher performance interconnects. They may prefer a high density interconnect, so we offer a different interconnect system for the SoC products providing fewer metal layers if low cost is important, or more metal layers if increased interconnect density is important." Bohr adds, "Next we provide a range of advanced passive device elements, such as precision resistors, capacitors and high-Q inductors, and a range of embedded memory from the very smallest, dense SRAM cells to low voltage SRAM, to high speed SRAM. For our SoC product design, we offer this rich mix and match feature set."

In general, Intel plans to stay on its well established two year cadence, but moving to a dual platform approach, introducing both a CPU-specific and SoC-specific version of each technology. Production of 32nm products is just starting this year: the end of 2011 should see 22nm products, with 15nm introduced at the end of 2013. How soon will we see some of the more exotic technologies, such as graphene and spintronics, in volume production? Not soon, given the conservative nature of the industry. Instead, it's going to be all about integration.

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