Ultratech: Melt LSA at sub-16nm, readying for FinFETs
As the semiconductor equipment industry looks ahead to what it hopes will be a much better economic picture going forward than in the past year or so, Ultratech's chairman/CEO/president, Art Zafiropoulo, updated SST on the company's strategy and focus.
Last year, Zafiropoulo alluded to an alpha tool with which customers were characterizing melt laser spike anneal (LSA) technology. Today, customers are still evaluating melt technology at 22nm, 16nm, and even sub-16nm nodes, he notes. "When they establish the [process] conditions, we'll start to manufacture the actual production melt system," he says. Ultratech still expects a transition from sub-melt LSA to melt LSA at around 22nm with more emphasis placed on melt technology at 16nm.
"We still believe that LSA technology is extendible to 22nm," Jeff Hebb, Ultratech's VP of marketing told SST. End users have been trying to refine their 40/45nm and 32nm processes, and the issue of leakage has worsened. Mobile applications (e.g., smart phones and netbooks) require both high performance and low leakage, dual requirements that are proving to be serious challenges and must be met simultaneously.
LSA can go to higher process temperatures that increase junction activation—forming more abrupt junctions—so, leakage is lowered. The higher process temperatures are possible because only a very thin surface layer of the wafer (where the transistors are formed) is heated. Furthermore, dwell times (at elevated temperature) are very short; annealing times can be on the order of milliseconds, microseconds, or, at the melt condition, nanoseconds. And while HK+MG itself reduces leakage by a factor of ~10×, "LSA provides extra leakage reduction that is additive, so you get an additional 3×-5× reduction in leakage" plus that of HK+MG, Hebb told SST.
|Normalized overlay errors for 32nm device wafers vs. LSA dwell time. Reducing the dwell time from 800μsec to 275μsec reduced overlay errors by 60%. (Source: Ultratech)|
Another major concern at advanced nodes is lithography overlay error. Because LSA is able to keep stress in the wafer low—only a small portion of the wafer at any given time is heated and the dwell time is short—it is able to meet the ever more stringent lithography overlay error requirement (see figure), Hebb explained. And when the industry is ready to move to FinFET structures, LSA is extendible. "We think millisecond annealing tools will be challenged to deal with FinFETs," he said. — D.V.