Optimization of edge die yield through defectivity reduction
Executive OVERVIEW In the pursuit of maximum production efficiency, advanced semiconductor manufacturers are developing strategies to improve the yield of devices all the way to the wafer's edge. The ITRS shows edge exclusion decreasing from 3mm to 2mm currently, and to 1.5mm in the future , ultimately producing more dies out per wafer. This reduction in edge exclusion, along with several other process trends, is exacerbating edge-related productivity issues, making edge-related defects a priority for IC manufacturers. Here, we examine several approaches to reduce wafer edge defect sources.
In the pursuit of maximum production efficiency, advanced semiconductor manufacturers are developing strategies to improve the yield of devices all the way to the wafer's edge. The ITRS shows edge exclusion decreasing from 3mm to 2mm currently, and to 1.5mm in the future , ultimately producing more dies out per wafer. This reduction in edge exclusion, along with several other process trends, is exacerbating edge-related productivity issues, making edge-related defects a priority for IC manufacturers. Here, we examine several approaches to reduce wafer edge defect sources.
Kalyan Jami, Srini Vedula, Gerry Blumenstock, KLA-Tencor Corp., Milpitas, CA, USA; Jack Chen, Keechan Kim, Yunsang Kim, Yung Kim, Lam Research Corp.,Fremont, CA USA
One prominent trend is the introduction of immersion lithography in production with thin-film stacks that now extend beyond the wafer bevel and which increase the risk of edge delamination. Since the outer 20mm of a 300mm wafer can contain up to 25% of the wafer die, edge-related defects are a serious yield concern. For example, a recently published benchmark study demonstrated that yields can decrease by as much as 50% at the wafer's edge because of defects . The economics of semiconductor production dictate that new efficiencies must be constantly found to support the needs of the market. As a consequence, the wafer edge region is emerging as a key focus area in process optimization and control.
Chipmakers are implementing several approaches to reduce wafer edge defect sources. Most manufacturers are inserting bevel clean steps into the process flow using a dry (plasma), wet, or polishing process. Integrating new bevel cleans into production involves selecting appropriate insertion points in the process flow, optimizing the clean processes, and achieving production control through repeatable performance. Wafer edge inspection and metrology techniques are being used to assist in identifying these insertion points and expediting bevel clean optimization.
The bevel clean technology should provide tunable selectivity, process flexibility, and efficient cleaning of the wafer's edge without inducing damage or redistributing defects to the active die region. Productivity should also be considered, such as the ability to clean multiple layers sequentially in the same process module. Plasma-based bevel cleans are particularly attractive in that they can easily fit into the process flow for a range of applications, including post-shallow trench isolation (STI), post-gate, post-bitline, post-damascene etch, and pre-immersion lithography.
For effective defectivity characterization, the edge inspection equipment needs to provide sub-micron particle sensitivity, a wide range of defect type capture, accurate classification, in situ defect review capability at high resolution, and defect statistical analysis and reporting features. An on-board, high-resolution optical review microscope or camera is also important to assist in defect identification and timely process feedback. Edge metrology capability should include complete360° edge coverage with accurate measurement of multiple films and automatic data upload for advanced process control (APC).
Wafer edge defect sources
The wafer's edge bevel region is a geometric discontinuity from the wafer's planar surface. As illustrated in Fig. 1, several regions must be managed—the near-edge (5mm), bevel, and apex. In addition, there are several mechanisms for edge-related defect generation and migration, resulting in frontside contamination and potential yield loss.
Figure 1. Schematic illustrating wafer edge regions to be managed, and mechanisms of edge-related defect generation and migration.
New materials, such as porous low-k and organic films, often do not adhere as well as traditional silicon- or polymer-based films—particularly at the wafer's edge—and can be significant defect sources. Tensile films, such as amorphous carbon, may adhere poorly at the edge of the wafer and can peel off in long strips that tend to ball up, creating particle sources. In immersion lithography, fluid forces generated by rapid stage movements can delaminate film edges or dislodge embedded particles, and the fluid provides a transport mechanism. Debris can migrate from the edge to the active area, impacting yield; to the wafer backside, causing exposure hot spots; and to the wafer stage, resulting in extended scanner downtime.
As shown in Fig. 1, a variety of defects can be generated at the wafer's edge, including scratches, cracks, and chips due to mechanical handling; blisters, flakes, and peeling due to thermo-physical film or polymer stress; and residues and particles from processes such as CMP, clean, etch, and immersion lithography. Particles can then be trapped on the edges of the film and/or in the crevices of scratches and chips.Edge-generated particles and residues can also be transported by gas or liquid flow during subsequent process steps. Defectmigration may result in yield loss due to the deposition of defects in the active die region or contamination of theequipment (such as particle contaminants in the immersion fluid).
Bevel clean process optimization
Edge inspection is used at various points in the manufacturing process flow to identify bevel defects. Once a problematic module has been identified, optimizing the insertion of a new bevel clean step typically involves an iterative process. The most common strategy is to tune bevel clean processes at several insertion points. Defectivity inspection data and analysis are then used to identify the most effective places to add new cleans (Fig. 2a).
Figure 2. a) Flow chart reflecting edge defectivity management and control methodology; b) Defectivity map taken on a KLA-Tencor VisEdge wafer edge inspection system showing a perimeter defect after etch; c) Specular channel image from VisEdge optical inline metrology (left) and SEM inspection (right) identify the defect as a microtrench.
The effectiveness of this approach is demonstrated in the example for a front-end-of-line (FEOL) post-etch bevel clean. A pre-clean edge inspection revealed a dark gray line around the perimeter of the wafer at approximately 1.0 to 1.4mm from the edge (Fig. 2b). Inline optical metrology images and SEM review (Fig. 2c) identified the gray band as a microtrench, which can become a killer defect in subsequent process steps. A plasma-based bevel clean was then performed, targeting film removal from the wafer's edge to 1.4mm from the edge.
Similar to a plasma etch process that selectively removes material from the die pattern, plasma-based bevel clean technology has the ability to target a defined edge region while protecting the active area. Four bevel clean processes were tested and their effectiveness evaluated through wafer edge inspection. Results for these splits are shown on the edge defectivity wafer map in Fig. 3a. Optical metrology and SEM review show that process condition 4 resulted in complete removal of the microtrench feature (Fig. 3b, left) and the smoothest silicon surface (Fig. 3b, right).
Figure 3. Results of bevel clean optimization performed on a Lam Research 2300 Coronus plasma-based bevel clean system. Defectivity map for the process splits (a), optical metrology (b, left), and SEM review (b, right) show that Process 4 resulted in full removal of the microtrench defect and the smoothest surface.
Implementing a plasmabevel clean has been shown to reduce electrical failures in STI modules , and manufacturers implementing plasma bevel cleans have reported up to a 5% improvement in overall electrical yield on 300mm wafers .
Inline metrology can be effective for monitoring and controlling edge exclusion for bevel clean processes, as well as other edge-impacting processes, such as lithography edge bead removal (EBR), film deposition edge coverage, backside rinse, and CMP edge coverage. After multiple layers have been deposited, edge film measurement is more challenging due to multiple EBR lines, pattern noise, thickness, and topographic and color variations. To provide accurate results under these conditions, a multi-channel, automated, complete 360° edge metrology system—running simultaneously with defect inspection—is required.
Typically in produc-tion, the repeatability of a bevel clean process is monitored daily on a statistical process control (SPC) monitor wafer or, if possible, after every lot on production wafers. An APC loop can also be used to provide real-time feedback. With APC, should a wafer fall outside the specified control limits, the inline metrology tool can feed the output back to the bevel clean system so that corrective action can be taken. The parameter generally measured is the bevel clean distance (BCD), which indicates the distance from the wafer's edge that was cleaned.
|Figure 4. a) VisEdge Mercator plots for two 300mm monitor wafers after 2300 Coronus plasma bevel clean. b) Bevel clean distance (BCD) SPC data show improved performance with post-metrology feedback correction.|
In Fig. 4a, a circular scan region of a 300mm wafer has been unfolded into a 2D Cartesian (Mercator) plot from 0° to 360° on the x-axis. The y-axis indicates distance from the wafer's edge. The BCD line tracks the edge of the clean region (film edge) as measured by the green line, while the wafer edge is traced by the red line. If the wafer is perfectly centered, the BCD line will be straight. With increased wafer centering offset, the BCD line will devolve into a sinusoid, where the magnitude is the offset distance from the average as measured by the concentricity parameter from the metrology tool. Similarly, if the removal step is uniform, the edge trace will be smooth; however, if the bevel clean process causes rough edges, a high frequency variation would result, which can be captured by the standard deviation value.
An example of process monitoring is given in Fig. 4b, which shows the average, minimum, and maximum BCD for a 300mm plasma bevel clean process on monitor wafers. The results for wafer #1 have fallen outside the specified control limits. The circular scan results in Fig. 4a indicate that an offset adjustment in the bevel clean process is needed. Using a feedback loop, the offset magnitude and direction information was fed into the bevel clean system to recalibrate the wafer handler and correct for subsequent wafers. This post-metrology feedback correction is demonstrated by the tighter BCD ranges shown in Fig. 4b. The improved bevel clean performance can also be seen in the Mercator plot; for example, wafer #5 in Fig. 4a. An APC feedback loop as described can automate the handling of common process shifts so they are quickly identified and corrected in production.
With increasing need to reduce edge exclusion and improve edge die yield, more attention is being paid to managing the wafer edge region. Wafer edge defect monitoring can be used to identify defect sources and quantify potential edge die yield loss. With this information, plasma-based bevel clean processes can be used to selectively remove edge defects while protecting the active die area. Determining appropriate insertion points for new bevel cleans and optimizing those processes typically involve an iterative approach, which can be accelerated with appropriate edge inspection and metrology methodologies. Inline metrology that provides APC feedback to the bevel clean system offers an added control capability for production processes.
VisEdge is a registered trademark of KLA-Tencor Corp. 2300 is a registered trademark and Coronus is a trademark of Lam Research Corp.
International Technology Roadmap for Semiconductors, 2007 edition; www.itrs.net
F. Burkeen, et al, "Visualizing the Wafer's Edge," KLA-Tencor YMS Magazine, Winter 2007.
V. Vahedi, M. Srinivasan, and A. Bailey, "Raising the Bar on Wafer Edge Yield–An Etch Perspective," Solid State Technol., November 2008
A. Bailey, L. Archer, J. Allen, "Bevel Cleans Enhance Yields by Controlling Edge Defect Sources (sidebar)," Semic. Intl., August 2008
Kalyan Jami received his B. Tech in electronics and electrical engineering (microelectronics), and is a product marketing manager at KLA-Tencor Corp., One Technology Drive, Milpitas, CA 95035 USA; 408-666-2653; email@example.com.
Srini Vedula received his BS in chemical engineering from the Indian Institute of Technology, Mumbai, and his PhD in chemical engineering from the U. of Tennessee, Knoxville. He is a product marketing manager at KLA-Tencor Corp.
Gerry Blumenstock received his MS and BS in physics from the U. of Maryland, and is senior director of marketing for the SWIFT Division at KLA-Tencor Corp.
Jack Chen received his BS in mechanical engineering and his MS and PhD in electrical engineering from the U. of Illinois at Urbana-Champaign, and is a process engineer at Lam Research Corp.
Keechan Kim received his BS in chemical engineering from POSTECH and his PhD in chemical engineering from the U. of Florida, and is a senior process engineer at Lam Research Corp.
Yunsang Kim received his BS and MS degrees in materials science from Inha U., and is a technical director at Lam Research Corp.
Yung Kim received his BS in electronic materials from the University of Kwang Woon, and is a technical marketing director at Lam Research Corp., 4650 Cushing Parkway, Fremont, CA 94538 USA; 510-572-6265; firstname.lastname@example.org.