Copper interconnect advances to meet Moore's Law milestones
To date, scaling has been enabled by thinner films, new materials, and new process flows (e.g., strain engineering and ultra-violet curing). Innovations have focused on enabling manufacturers to achieve greater functionality per unit cost. Current development work shows viable extendibility of chemical vapor deposition (CVD) of ultra-low-k dielectrics and low-k barrier materials, physical vapor deposition (PVD) of diffusion barrier/copper seed layers, and gap fill technologies. Containing production costs while sustaining the pace of Moore's Law through 2X/22nm, however, may necessitate adoption of three-dimensional (3D) interconnects in mainstream device design and fabrication. 3D interconnects allow continued 2D scaling through extension of existing process technologies without the need to invest in more expensive lithography solutions.
Ajay Bhatnagar, Mehul Naik, Sesh Ramaswami, Matthew Spuller, Michael Armacost, Russ Perry, Jim Van Gogh, Jen Shu, Gary Miner, Applied Materials, Santa Clara, CA, USA
As device geometries have continued to shrink, copper has displaced aluminum as the standard back-end-of-line (BEOL) enabler of lowering overall power consumption and operating temperature, and increasing device speed through reduced resistive-capacitive (RC) delay. Although switching from aluminum to copper is more complex in DRAM and Flash devices, copper's advantages have led memory manufacturers to implement this transition in 4x/45nm production. As scaling continues beyond 4x/45nm, however, achieving the requisite device performance and reliability will demand much more from interconnect materials, processes, and integration schemes, with attendant increases in production costs.
Copper in logic and memory
Copper has been standard in logic devices since the 130nm node. In the last two years, copper's lower resistivity compared to aluminum has made it attractive to memory manufacturers, spurring advances in copper barrier/seed and filltechnologies.
For both segments, the constant challenge is the co-optimization of RC delay and reliability. RC reduction for logic has been enabled with advances in low-k and ultra-low-k (ULK) films and dielectric barriers. These integration-proven materials achieve the required RC delay with interface properties that accommodate further capacitance reduction and meet reliability specifications. For memory, bit-line capacitance reduction has been achieved through reduction of bit-line height, enabled by the lower resistivity of copper.
Higher operating voltages in Flash devices compared to logic devices have placed more stringent requirements on meeting time-dependent dielectric breakdown (TDDB) specifications. These demands have driven development of dielectric barriers that maintain low resistance of the circuit through surface preparation and enable high electromigration (EM) lifetime (>10 years). This work has also been useful in developing lower k dielectric barriers required for logic.
Extending 2D copper interconnect
Recent development work demonstrates extendibility of CVD ULK dielectric and low-k barrier materials, PVD diffusion barrier/copper seed, and gap fill technologies to 3x/32nm and beyond. Advances in enhancing porous low-k film properties, engineering interfaces, and optimizing ashing/precleans are meeting the aggressive device performance and electrical reliability specifications for these nodes.
Dielectrics. In logic, the push to 32nm devices incorporating porous low-k materials has required a holistic approach to the RC challenge. While the porous low-k material used is similar to that at the 45nm node, significant advances in lower-k dielectric barriers and etch processes, and the growing adoption of hard-mask based schemes have all contributed to lowering the effective k value.
|Figure 1. ULK (k=2.2) and barrier (k=4.0) with 12:1 etch selectivity meet aggressive 22nm specifications.|
Porous low-k materials in development for the 32nm technology node and beyond are currently achieving a dielectric constant of k = 2.2, while maintaining the mechanical strength and etch/ashing damage resistance characteristics of porous SiCOH filmsfor 45nm (Fig. 1). The greater porosity of thefilm presents integration challenges, such as sidewall attack from un-optimized etch/ashing processes or potential for bottom anti-reflective coating (BARC) poisoning. Although higher carbon content lowers the dielectric constant, it degrades mechanical strength by reducing the ratio of Si-O networking to Si-CH3 bonding.
To meet these challenges, new precursor screening has been successful in identifying a novel chemical route for enhancing mechanical strength at k = 2.2. Concurrently, work is being done on reducing pore-to-pore connectivity and potential for low-k damage, as well as improving UV curing to enhance the properties of porous low-k films. With these improvements, porous low-k technology, currently proven for production at most foundries and logic customer sites, is expected to extend to 22nm. A leading logic company has demonstrated more than 8.5% capacitance improvement withk=2.2 porous low-k.
Potential new barrier materials can further reduce the effective k value by enabling thinner films while maintaining good barrier properties with respect to moisture, copper diffusion, and oxidation resistance. Novel schemes are also being explored to enhance the integrity of the copper interface for improved electricalperformance and reliability by adding an engineered surface layer.
Etch. In both logic and memory, critical dimension (CD) and depth control specifications are becoming increasingly stringent (<3nm CD non-uniformity). These metrics are being met by enhancing the ability to tune uniformity from wafer center to edge by manipulating the neutral and ionized species. In logic, etch-induced damage to low-k sidewalls must be minimized (<2nm/side) through optimization of ash chemistry and use of restoration techniques. Different integration schemes also present unique challenges. Conventional via first etch processes must etch sub-50nm features without toppling the photoresist (PR) mask required to image the dielectric. Alternatively, metal hard-masked schemes must pattern and maintain tight CD control while minimizing yield degradation resulting from metal contamination.
These challenges have been met by appropriate chemistry tuning and chamber cleaning. For 22nm, meeting the required CD targets will require etch trim steps to shrink PR dimensions after lithography.
Copper barrier/seed. Recent breakthroughs in PVD copper source technology are expected to extend PVD to the 2x node. Further innovations in manipulating ion and thermal energies may extend PVD viability even further. Alternative technologies combining atomic layer deposition (ALD) and CVD processes are also being pursued to extend copper barrier/seed metallization to 1x and below.
Development for 3x/2x has focused on meeting demanding TDDB requirements for barrier materials and heightened aspect ratios (4:1) that affect conformality, step coverage, and symmetry. Both tantalum and less costly titanium perform well in meeting barrier requirements. PVD source innovations have enabled conformality of thinner layers while chemical modification has enhanced adhesive properties. Beyond 2x, barrier enhancement may be necessary to optimize resistivity, effectiveness as an oxidation barrier, and adhesion of an even thinner seed layer. For this, CVD cobalt is the leading candidate in performance and cost-effectiveness.
|Figure 2. Highly conformal, continuous PVD barrier/seed layer deposition enables void-free gap fill at 2X/22nm.|
Overhang in barrier/seed layers can seriously reduce seed layer step coverage. At 2x, even minute overhang can almost completely occlude the trench from the target. Innovations in magnetron motion and flux control with a high resputter ratio process are creating smooth, continuous copper seed for void-free gap fill and optimum device reliability (Fig. 2). This process offers a compelling cost advantage by preserving current, well-characterized process flows.
Despite advances in conventional interconnect fabrication, the industry is approaching the point at which 3D integration approaches may be required to cost-effectively realize the functionality/transistor count increase expressed by Moore's Law.
3D integration is an umbrella term applied to the methods of vertically connecting several chips to achieve the highest performance and functionality in the smallest package, using established CMOS technology and micro-fabrication methods. To date, 3D integration has been accomplished for specialized applications using wire bonding and flip-chip stacking; however, through-silicon via (TSV) technology is rapidly emerging as an alternative method offering more layout flexibility, and greater energy and space efficiencies than wire bonding and flip chip stacking. In TSV (also known as 3D interconnect), a bonded stack of chips is joined by vertical interconnects running through one or more wafers and functioning as components of the integrated circuit.
TSV's advantages are substantial: shorter interconnects, lowerpower consumption, faster device switching, and much higher input/output density. TSV also enhances the functional integration of homogeneous or heterogeneous chips; each device could originate from different fabs or be from completely different technology nodes, thus allowing flexibility in supply chain and scaling. These factors enable TSV to boost memory capacity per unit board area (e.g., for DDR4 DRAM), or speed up data exchange between processors and other components in communications and mobile Internet devices.
TSV processing commences in the front-end fab, typically at middle-of-line on full thickness wafers, or in the back-end from the backside of thinned wafers. Although the taxonomy is still under development, the manufacturing processes may be generically classified as via first and via last, respectively. In either case, the key wafer process steps are: TSV etch, dielectric deposition, barrier/seed deposition, copper fill, and planarization. Wafers are typically bonded to carriers (glass or dummy silicon) and thinned to a thickness ranging from 30 to 125µm, which introduces newmanufacturing challenges, including thermal budget control. To preserve the adhesive integrity of the bonding material once wafers are bonded, processing temperatures cannot exceed 200°C.
|Figure 3. Highly selective etch technology enables both high etch rates and the profiles (negligible scallop, taper, or undercut) essential for depositing the high-quality liners (right) required for conformal barrier/seed layers and good copper fill.|
Key considerations for a successful etch are via profile (taper, undercut, scallop), high etch rate, and selectivity for aspect ratios ranging up to 10:1 (Fig. 3). A process highly selective to PR eliminates the need for a hard mask and lowers costs. A good profile is essential for the successful downstream processing (liner and barrier/seed deposition, and gap fill).
The dielectric liner is the electrical isolation between silicon and copper. The liner must be highly conformal to provide a direct line-of-sight to the target in the subsequent metal barrier PVD process. Re-entrant profiles lead to poor metal barrier/seed coverage and incomplete copper gap fill. The dielectric liner must also adhere well to the underlying silicon and subsequent diffusion barrier. Uniformity and film quality are also essential for managing capacitance and crosstalk. Sub-atmospheric pressure CVD liners provide >75% sidewall coverage on these high aspect ratio vias, with excellent film quality and adhesion to both silicon and tantalum/titanium barriers. Using these techniques, films thicker than 1µm can be deposited with high throughput.
Depositing the barrier layer and subsequently filling the via with metal are among the most challenging and expensive processes in the TSV flow. A good copper diffusion barrier (e.g., tantalum or titanium) is needed, and a continuous seed layer is crucial for good copper fill. The fill process must provide both a high fill rate (to lower cost) and good fill characteristics with across-wafer uniformity toenable good post-planarization surface characteristics.
With these unit processes producing generally good performance, present development work is focusing on integrating the manufacturing value chain (i.e., thinning, bonding, and on-wafer processes) to accelerate mainstream adoption of TSV by optimizing overall cost and mitigating end user risk.
Increasingly used in memory devices, copper processing is also evolving to address gap fill extendibility and barrier enhancement demands. Dynamic on-wafer process innovations are enabling manufacturers to adhere to the semiconductor industry roadmap. Concurrently, techniques are emerging for integrating 3D interconnects to maximize functionality in the most compact form factor. Merging these two directions should enable the industry to cost-effectively fulfill Moore's Law for several device generations to come.
Ajay Bhatnagar received his PhD in materials science and engineering from Stanford U., and is global product marketing manager in dielectric gap fill at Applied Materials, 3050 Bowers Avenue, Santa Clara, CA 94054, USA;firstname.lastname@example.org
Mehul Naik received his PhD in chemical engineering from Rensselaer Polytechnic Institute, and is a distinguished member of technical staff at Applied Materials.
Sesh Ramaswami received his MS in chemical engineering from Syracuse U. and MBA from San Jose State U., and is senior director, strategy and marketing, and TSV program manager at Applied Materials.
Matthew Spuller received his PhD in chemical engineering from Georgia Institute of Technology, and is global product marketing manager at Applied Materials.
Mike Armacost received his MS in chemical engineering from Clarkson U., and is senior director of customer technology in the etch products business group at Applied Materials.
Russ Perry received his MBA from Chapman U., and is the director of product marketing for the Blanket Dielectric Division at Applied Materials.
Jim van Gogh received his MBA from Santa Clara U., and is the managing director of global product management in the metal deposition product group at Applied Materials.
Jen Shu received her PhD in chemical engineering from Cornell U., and is director of technology at Applied Materials.
Gary Miner received his MSEE from Stanford U., and is the chief marketing officer for the metallization product and the front end product groups at Applied Materials.