Understanding tester interfaces
From a signal integrity point of view, there are generally four classes of problems with the test cell and DUT interface: impedance mismatches, crosstalk, transmission line losses, and inadequate power distribution. This article provides "hands-on" insight into each.
Nick Langston, Liberty Research, Cupertino, CA, USA
Due to the insatiable appetite for bandwidth, chip vendors are leveraging serialized, asynchronous architectures with serialized data channels rather than the classical synchronous parallel busses. The current generation of devices has data rates to 6.25Gb/s and 10Gb/s. There are also large ASICS that have core logic switching at multi gigabits. They switch tens of amps in less than 300ps, pull down the voltage rail, and generate excessive noise in the signal and return paths. Memory devices that have multiple asynchronous busses are common—they could switch up to 72 outputs simultaneously in less than 0.5ns.
These speeds and high currents make it imperative for test engineers to view the test cell not as a combination of unrelated components but as an integrated system if they are to produce the highest yields and lowest cost of test.
The integrated system includes the ATE boards, stiffeners, test sockets and docking kits and handling systems. If any of these components are less than optimal, yield control could be a challenge. For example, if the device nest is not compressing the device/contactor enough, the Pb-free solder balls have pin plating defects, the board has excessive dielectric losses, or when the socket contributes to crosstalk, yield will be reduced. Without a clear understanding of the system components, it may be difficult to isolate the cause.
Signal integrity issues
A robust integrated system design requires precise mechanical knowledge and, increasingly, an awareness of signal integrity issues and how the elements impact each other. From a signal integrity point of view, there are generally four classes of problems with the test cell and DUT interface: impedance mismatches, crosstalk, transmission line losses, and inadequate power distribution. Generally, impedance mismatches on a transmission line affect the edge rate and cause reflections. These discontinuities can be caused by many things, including variations in the trace's cross-section or a trace's distance to the reference plane. Vias can also appear as a discontinuity and a capacitive reflection.
|A test cell, including the test head, load board, test socket, and auto DUT handler.|
If the signal path had only one impedance mismatch, it would pose few problems; however, when the reflected energy hits any other discontinuity, it re-reflects. Likewise, any reflection coming from the DUT re-reflects when its energy hits the input via. These reflections and re-reflections will continue to bounce back and forth until they are totally dissipated. The magnitudes of the reflections depend entirely on the reflection coefficient (r).
The most effective way to evaluate a transmission line is by displaying the signals in an eye diagram. A simulator, such as Mentor's Hyperlynx, lets you select the appropriate IBIS model and generate a PRBS to run against the network. The location of the reflections and re-reflections is strictly a function of the electrical distance between the Zo mismatches. Therefore, the effect on the data eye is a function of this electrical distance and operating bit rate. When mismatches are electrically close relative to the bit period, the reflection and re-reflections degrade the data eye amplitude with perturbations. As the electrical distance between the launching and the DUT increases relative to the bit period, the reflections start to add deterministic jitter.
The classical technique to analyze impedance discontinuities is to use the Lattice or, more commonly, the Bergeron diagrams. But it can get rather tedious and subject to error, so the wiser choice is to use a simulation tool.
Vias and impedance
Due to ever-increasing pin densities, DUT board vias are a special case of impedance mismatches that require attention. ATE boards are rather thick (usually 0.2") and the vias are very long when going from the bottom of the board to the top. As a result, they can add a fair amount of inductance to the signal and return paths. The jitter from impedance discontinuities in the vias will reduce the eye opening as much as 3dB and create a large amount of jitter.
The capacitance of a via depends on the dimensions of the pad, hole diameter, clearance on the ground layers and, of course, the board thickness. A signal sometimes traverses only a portion of the via length and connects to an inner layer. The differential portion of the via looks like an unterminated capacitance and a "stub" to the signal, which will have a negative effect on the edge rate and create an additional impedance discontinuity. To eliminate the stub, back-drilling is used to remove the excessive via length. Another approach to minimize the reactance of dangling vias is to construct a via that only travels to the connected layer. This technique uses sequential lamination of layers to create "blind" vias, which are a rather expensive option when you need to make a 28-layer board. But they can improve signal fidelity significantly.
Transmission line losses
When designing a load board for gigabit/s speeds, you must account for the lossy effects in the transmission lines. Rigorous analysis of losses is necessary because they are normally a first-order effect that significantly degrades the performance of the interconnects. Degraded rise time is the dominant impairment that transmission-line losses create.
|Figure 1. Lossless (top) and lossy (bottom) transmission lines.|
The basic model for a lossless transmission line is shown in Fig. 1. The equation for the characteristic impedance of a lossless transmission line is Zo = L/C 0.5. This model works well enough for boards that operate at frequencies below 900MHz. As the frequency or the harmonics get high enough, however, those losses become significant and have negative effects on board performance.
There are two categories of loss that we need to be concerned about. The schematic Fig. 1 (bottom) identifies both of these, represented by Rz and the Gz in the model. Rz represents frequency-dependent skin effect losses associated with the resistance in the trace metal, and G represents the frequency-dependent conductance losses associated with dielectric absorption. Dielectric absorption (aka, dielectric loss) is the amount of energy that is absorbed into the dielectric material.
|Figure 2. Plot of conductor losses for three different trace widths, and dielectric losses for five different materials. (Johnson and Graham, 1993)|
The graph in Fig. 2 plots the loss caused by the skin effect (blue line) in the copper of the trace. You can see that the loss increases as the square root of the frequency. At 1GHz, the loss is equal to 1.5% per inch, while the dielectric (red trace) is at 1.6% per inch of trace in FR4. At 5GHz, the loss due to skin effect is 3% per inch while the dielectric has increased to 7% per inch for a total of 10% loss per inch. Above 1GHz, the dielectric losses dominate over conductor losses. When the material exhibits high dielectric losses, the losses introduce an additional problem in the data-dependent jitter caused by the slowing Tr. This is known as Intersymbol Interference (ISI).
|Figure 3. A comparison of FR4 to Getek.|
The waveform in Fig. 3 shows the data eye with a bit cycle of 200ps. The trace, which is 50.2W in FR4, is compared to a 53.3-W trace with the same length using a Getek dielectric. The trace geometries and dielectric thickness are the same; the only thing that was changed is the dielectric used—FR4 and Getek. The difference in the loss tangent of the dielectrics caused the propagation change as well as the impedance change. What is noted is that the 3-W difference balances out the jitter results. But the loss of the FR4 is about 1dB more than the Getek.
Inductances, particularly from the vias, connectors, and test sockets are the major culprits in supply noise. In bus devices, when the outputs switch currents through excesive channel inductances, simultaneous switching noise (SSN), or delta I noise, is generated. The more outputs that switch, the more crosstalk and noise that will be developed. A method to reduce the inductance of the vias, at least on the outside row of a BGA, is to place ground vias adjacent to every I/O via. This will provide a very short return path and will counter other inductances.
Power distribution network
The primary function of the power distribution network (PDN) is to provide the necessary power to the components on the board, more specifically the DUT. All digital devices have a requirement on all the supplies that they not fluctuate more than +/- 5% from the nominal value. The DUT activity will vary, and the supply current will vary according to the demands on the device. As large sections of the device are turned on, the current requirement will increase and the frequency ofthe current demand will vary across the spectrum.
|Figure 4. 2.5Gb/s on 8" of FR4 with two vias.|
The problem is when the output buffers switch, they try to draw current from the supply as quickly as possible. But the supply isn't ideal and cannot possibly source an infinitely large amount of current in an infinitely small amount of time. The series inductance in the supply path will limit the amount of current available during switching times. The current has to be pulled through the inductance of the vias of the board, and then the inductance of the pogo pin in the socket. If the inductance is high enough, it will starve the device output of current, at least temporarily. The voltage at the I/O will drop and the ground will bounce, and the rise time/fall time will be seriously impaired.
To calculate the maximum tolerable inductance of the board and socket: Lmax ~ DV/2pFDI.
If you plug in the numbers for a high-speed bus-type memory with 1ns Tr, and each output sinking 30ma into a via—the max L you can have is 4nH. With a 500ps Tr , you are down to 2nH max board and socket total inductance. Ideally, the test engineer can reduce the major part of the series inductance by arranging the stack-up and position of the Vcc/Vss planes to be close to the surface, or reducing the board thickness or minimizing the length of the socket pogo pins. In addition to reducing the series inductance, decoupling capacitors (caps) need to be placed as close to the net as possible. Decoupling caps serve as a reservoir of current available very quickly to the DUT when it switches. There are several techniques proposed for choosing decaps. The figure of merit for a decap is its equivalent AC impedance, estimated by using a root-mean-square approach, including the impedance of the R,L & C:
Xac(F) ~ R2ESR + (2pFL – 1/2pFC)2 0.5
The caps need to be selected to provide a low impedance at the operating frequency. But no matter how much decoupling you have on the bottom of the board, it is too far away and you will be bandwidth-limited. At Liberty Research, we've actually put decoupling caps in the socket to reduce the distance.
An important element in obtaining low impedance for the supply is to have sufficient Vcc-Vss pairs in the package. When there are too few, it requires more current going through fewer pins and causing proportionally more noise. As socket pins get contaminated by the solder, the resistance goes up and fewer pins will carry the load, causing additional noise. The selection and placement of the decoupling caps is critical to the optimal performance of the chip.
Nick Langston heads up Liberty Research, a consulting company that offers outsourcing of test cell solutions. He previously held positions at Antares, Accutest, Megatest and Tektronix. Liberty Research Co., 19925 Stevens Creek Blvd., Cupertino, CA. 408-725-7139; email@example.com