Intel Research Day: Update on EUV, other projects


Research at Intel Labs covered at the chipmaker’s annual event (June 18, Mountain View, CA) covered the major categories of eco-innovation, 3D graphics on the Internet, mobility, and enterprise. But Mike Mayberry, VP technology & manufacturing group director of components research, conducted a roundtable discussion that focused on the company’s manufacturing research, including a summary of the status of EUV.

Not surprisingly, Mayberry noted that EUV source technology is probably the most critical path item. In the “first wave” of tools (those used for R&D) so far, one of the beta sources can run a tool at ~10 wafers/hr, and has been run in burst mode at about 5X that speed, but has not yet proven that it can run a full year with only routine maintenance; also, the current class of scanners is running at ~1wph. The “second wave” of tools (for development) is expected to begin arriving next year. “So in principle, if you start development next year and it took two to three years to do development, that would place production in the 2012-2013 timeframe,” he said. Then a “third wave” of production tools would be required, though Mayberry would not speculate on how close together the second and third waves might turn out to be.

Intel has printed features down to 24nm using EUV, but it also knows how to extend 193nm down to that point by adding extra masks and extra cost to the wafer. “At some point they [193nm immersion and EUV] will cross over, so the world will not end if EUV is not ready by the time we get to this point,” Mayberry said, adding that various cost analyses suggest a cross-over point for memory just below the 32nm node.

The company can print features at ~35-40nm with one mask layer using 193nm immersion, and can go even smaller by employing “tricks” such as “doubling up on the masks,” Mayberry explained. “We can do other forms of adding information to the wafer that you can’t get through the optical system???so there are alternatives where you can go smaller.” Intel also has a lab demo setup that can print features (lines and spaces) at 15nm with 193nm litho, “but you can’t make a useful pattern with it in a single step,” he noted. So there are alternatives to EUV, but not necessarily better (if EUV is working as anticipated).

Regarding metals for interconnects, Mayberry explained that when the industry gets down to a 10nm wire, scattering around the surface will be the dominant effect. “We are weighing various options, such as how to engineer the surface, as well as the interaction between materials,” he said. “We’ll continue to push copper for a long time???but we’re already weighing alternatives to that so they’re ready when we need it.”

As usual, the familiar question about the end of Moore’s Law (and the implications if only one company can afford to stay on its path) came up during the roundtable. “People have been predicting the end of Moore’s Law for a long time...consolidation has obviously happened, but it’s always been slower and more unpredictable than people would have guessed,” explained Mayberry. He hesitated to predict how fast the consolidation will take place and who the winners will be, though he thinks Intel will be among that group. ??? D.V.