IITC 2009: Innovation in copper contacts, 3D, metrology
In its first foray outside of the US, IITC 2009 (June 1-3) took place in Sapporo, Japan, attended by some 600 scientists, engineers, exhibitors, and other interconnect professionals. The expectation, according to program chair Mike Shapiro, was that holding the conference in Asia will bring in papers that are more manufacturing-oriented vs. R&D only. “We didn’t have a lot of memory folks at IITC in California, but in Asia, we’re expecting more discussions about memory and consumer-type applications,” he told SST in a briefing ahead of the event. There is also an expectation of bringing in more materials and equipment suppliers, added Mike Armacost, publicity chair—and indeed, the conference has accepted more suppliers’ papers in general than in years’ past. (Shapiro noted that IITC 2010 will again be in San Francisco, but it is yet to be determined where the conference will be held in 2011; there have been discussions about bringing the conference to Europe.)
Shapiro (from IBM) and Armacost (Applied Materials) briefed SST on selected papers from the more than 80 technical presentations expected at the summer conference (see table). Additionally, a number of papers were to discuss line-edge roughness (LER), for which there appears to be a growing level of anxiety as the industry continues development of 22nm technology, Shapiro noted. Issues swirling about include concerns about lines having low enough resistivity, barriers starting to control the resistivity vs. the line/Cu cross-section, the roughness of the Cu, etc. While stopping short of admitting the industry will hit the red brick wall on the Roadmap, Shapiro noted he’s seeing indications this year that the industry is concerned about growing problems as the shrink continues.
Paper #2.4 from Semiconductor Leading Edge Technologies Inc. (SELETE) is significant, in that it’s one of the first times that EUV lithography has been used to make wires at 22nm, and that their properties have been measured. “As interconnects shrink, properties such as resistivity start to become questionable,” explained Shapiro. “This group was able to make very small wires that haven’t been made before and characterize them.” Researchers investigated these tradeoffs using EUV lithography, fabricating interconnects with widths of <40nm. They describe how they were able to achieve low effective resistivity of <4.5µΩ cm using PVD-Ru barrier film, vs. a more conventional Ta barrier, attributed to a combination of the barrier thickness, improved grain size, and filling capability of this barrier. The predicted circuit-performance using the Ru barrier was 10% higher than with the conventional approach, and the operating speed distribution was estimated to be <5% for the 22nm node CMOS generation.
NEC and Tokyo Institute of Technology researchers tackled the problem of matching logic and memory applications in via 3D interconnects (paper #10.4) by developing a 3D packaging technology called SMAFTI (SMArt chip connection with Feed-Through Interposer), which enables the implementation of a new memory/logic-interconnect hierarchy. The team implemented a new die bonding process and multilayer interconnect technology to form over a thousand parallel interconnects between memory and logic dies. They characterized the interlaminar horizontal wiring by S-parameter measurement up to 40GHz and confirmed its potential for high-speed signal transmission at over 10Gb/s. “The FTI is made in a novel way and how these things are attached is novel,” noted Shapiro. “The FTI has layers of metal and polyimide, which allows the memory and logic to be connected together, [and] can also make connections to the outside world.” Signal transport was measured between the logic and memory and across the FTI to make sure that the signaling met the application requirements, which Shapiro noted is fairly new for 3D interconnect structures.
Paper #2.2 is interesting, according to Shapiro, because the researchers use copper to replace tungsten to make contact down to devices (Figure 1). The adoption of Cu metallurgy for wiring interconnects is critical to meet RC requirements. Similar limitations of contact resistance are presenting challenges for engineers trying to get signals out of high-performance transistors. Cu has been considered for this application with some reluctance, because of the risk of device contamination.
The researchers, members of the IBM Alliance, used Cu contact metallization to demonstrate a fully functional 22nm node 6T-SRAM. Cu contact metallization was executed using CVD Ru-containing liner. Reliability data of a thermally stressing bulk device is discussed in the paper. Bulk device parameters such as junction/gate leakage currents and overlap capacitance were stable after BEOL anneal stress. Extendibility of Cu contact metallization to 15nm contacts was also considered. Though there has been concern with copper poisoning transistors, the researchers demonstrated device data and reliability data.
The helium ion microscope discussed in paper #6.2 was a surprise to Shapiro, and he suspects others are also not aware that the technique can be used for imaging low-k dielectrics. Researchers at Carl Zeiss SMT and SELETE developed a helium-ion microscope (HIM) that can be operated in three imaging modes. When low-k dielectric or copper interconnects are imaged in these modes, it was found that unique pattern dimension and fidelity information at sub-nanometer resolution are available for the first time (Figure 2). Shapiro noted that the technique is useful for imaging low-k dielectrics because the typical SEM charges the sample, which distorts the image. “With He ions, you don’t get the charging that distorts the image,” he pointed out. —D.V.