Inside Novellus’s tungsten CVD process for 32nm


Novellus says its new CoolFill tungsten CVD process offers a larger process window to achieve void-free fill that meets the ITRS’ electrical property requirements for 32nm DRAM and logic devices.

Specifically, the reduced-temperature (<395??C) CVD process directly addresses aspect-ratio challenges laid out by the International Technology Roadmap for Semiconductors (ITRS): >20:1 AR for stacked capacitor DRAM contacts, and >10:1 AR for logic devices. Achieving void-free fill that meets required low electrical properties in such aggressive features will be hard to do using conventional CVD tungsten deposition techniques, the company notes.

Cross-sectional TEM images comparing 32nm 18:1 aspect ratio contacts processed using standard and Novellus’ CoolFill CVD. (Source: Novellus)
Click here to enlarge image

Enter Novellus’ CoolFill process, which minimizes mass transport effects responsible for void formation. Used in concert, a “pulsed nucleation layer” (PNLxT) technology and “multistation sequential deposition” (MSSD) architecture on the company’s Altus CVD system, simultaneously deposit nucleation and fill layers at different temperatures, the company says. Combining lower-temperature feature fill with higher-temperature bulk fill mitigates the deposition rate and throughput reductions seen in conventional CVD systems. (A video animation of the multi-station sequential processing architecture is at

The CoolFill “provides a larger process window to achieve void-free tungsten fill” to simplify integration challenges in scaling devices to the next generation technology node, said Michal Danek, senior director of technology for Novellus’ direct metals business unit, in a statement. The combination of CoolFill technology with PNLxT and multistation platform architecture, he said, “will extend tungsten to the 32nm technology node and beyond.” —J.M.