Parallel probing universes draw closer


For the most part, the universes of wafer probes and sockets have customarily been separate and distinct. Yet they parallel each other in many ways: they provide temporary electrical contact to a device under test, and have many common technical challenges such as contact resistance, signal integrity, tight pitch, and cleaning, among others.

Despite similarities, it is uncommon to find engineers, suppliers, or test organizational structures involved with both. For example, there are probe engineers and there are socket engineers; probe suppliers and socket suppliers; and wafer test tooling, operations, and techniques, and those for package test. Even the languages of probe and sockets can differ. Jim Brandes, product manager at socket supplier Everett Charles Technologies, cited an example where in probes “overdrive” is the term, whereas in sockets it is “compliance”.

However, driven by the trend toward wafer-level packaging (WLP), where the package is fabricated alongside the wafer, distinctions between the two universes are diminishing.

In a keynote address at the recent Burn-in and Test Sockets (BiTS) Workshop, Karl Johnson of Freescale Semiconductor noted that historically in the semiconductor industry, “the magic was felt to be in the silicon, silicon processing, and in the design.” But as we move down Moore’s Law, “in the world of digital silicon, the assembly technology and packaging technology are now becoming an integral part of the overall system.”

Packaging has had a make-things-one-at-a-time feel to it compared to integrated circuits (IC) manufacturing, remarked Thomas H. Di Stefano, CEO/president of Centipede Systems, presenting at last fall’s International Wafer Level Packaging Conference (IWLPC). “The promise of wafer-level packaging is to break free of that constraint,” he said. “It allows us to process some, a portion of, or all of a package by similar methods used to process integrated circuits instead of one-at-a-time fabrication.”

With WLP, the traditional steps of less rigorous die-level wafer testing using probes, singulating the dies and packaging the tested good dies, then performing the more thorough package test and reliability screening with sockets are giving way. WLP enables a simplified process of conducting the more rigorous package test on the wafer and perhaps performing some reliability screening, then singulating the fully tested packages. If necessary, higher levels of reliability screening could follow. Eliminating die-level testing reduces test costs.

In this WLP process flow of package test at the wafer level, to contact the device under test, sockets (or contactors) are replacing the probes on a standard probe card, while other wafer test equipment — the probers, test heads, testers — remains unchanged.

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When asked why not continue to use wafer probes on WLP wafers, Brandes noted higher electrical performance, lower cost, higher compliance, easier maintenance, and a shorter leadtime for sockets, with the potential for Kelvin testing an added benefit.

Currently, the WLP die being tested using sockets are BGA devices with a low number of I/O’s and at relatively relaxed pitches. Cascade Microtech, one of the few suppliers offering both probe and socket products, is seeing RF devices move to WLP, according to Mike Kondrat, VP of marketing. Having both probes and sockets in the company’s portfolio, he’s looked at pitch to see where the best fit is for using sockets on WLP products. Currently at 0.5mm and even 0.4mm, sockets are the choice, with tighter pitch capability on the horizon.

Jon Diller of Interconnect Devices, a socket and spring pin firm, found that some customers had contacting issues using probe technologies on WLP wafers, so the probes were replaced with sockets using a common socket contact technology, spring pins. Even x4 and x8 multi-die testing is being achieved, he added.

Sure looks like the probe and socket universes are drawing closer.

—Fred Taber, general chairman of the Burn-in & Test Sockets Workshop