Issue



Copper BEOL solutions for advanced memory


05/01/2009







Robert H. Havemann, G. Andrew Antonelli, Greg K. Arendt, Michal Danek, Andrew J. McKerrow, Richard S. Weinberg, Novellus Systems, Inc., San Jose, CA USA

While most copper back-end-of-line (BEOL) memory applications today utilize a single damascene layer of copper for the bitline, there are growing applications that utilize multiple copper layers and dual damascene. To meet the needs of memory manufacturers as they transition to copper interconnects, new dielectric, metallization and planarization technologies have been developed, which allow extendibility to the 3X nm technology node and beyond.

Increased density and performance continue to be the key technology drivers for the semiconductor industry, and with respect to the interconnect, copper provides the best of both worlds: a more scalable damascene process architecture and a lower resistivity as compared with aluminum interconnects. Memory devices have recently started to take advantage of these benefits, and widespread adoption of copper interconnects is underway.

Integrating copper into memory devices presents a different set of challenges as compared with established logic process flows. DRAM and Flash comprise the majority of the memory applications and they exhibit very small CD sizes, high aspect ratios, and critical sensitivity to line resistance. Flash technology already has 3X nm size features in production, with 2X nm expected to begin pilot production at the end of this year. The small CD sizes along with trench aspect ratios >5:1 place extreme demands on managing PVD barrier/seed overhang while obtaining sufficient step coverage to ensure good fill during electro-chemical deposition (ECD). Barrier as well as seed overhang must be minimized to maintain margin prior to the ECD fill process. As the trench CDs can be as narrow as 22nm for the most advanced memory devices, there are strict limits imposed on the barrier/seed thickness at the top of the trench opening to ensure that the effective (“pre-plate”) aspect ratio prior to ECD is <10. Therefore, memory applications are driving the most challenging fill requirements for copper damascene.

While stringent via stress migration (VSM) and electromigration (EM) reliability remain critical prerequisites for logic devices, most memory applications run at lower power, and therefore, do not have the same level of thermal and electrical reliability metrics as those found in logic. However, due to the narrower linewidths used in memory devices, e.g., for bitline, interconnect line resistance has become a more pronounced metric, necessitating careful co-optimization of ultra-thin barriers and device reliability to meet line resistance goals.

For aggressively scaled memory devices, a further impetus for the transition to copper is the lower cost and manufacturability of damascene copper as compared with aluminum processes that may require a CVD Al liner to facilitate fill of small features. Because increased device density remains a key method for semiconductor manufacturers to effectively lower their cost per die, new materials and processes will continue to be required to enable scaling. So the overarching challenge for semiconductor equipment suppliers is to provide tools and processes that enable continued scaling and performance enhancement, while also providing improved productivity.

For the copper damascene structure, the challenge of copper fill begins with deposition of the copper barrier metal, which is typically a bi-layer of Ta/TaN, or in some cases, Ti(N). As feature size continues to shrink, a thinner barrier metal is required to maximize copper volume in the damascene structure and maintain reasonable effective resistivity of the interconnect.

For ultra-thin barrier metals, achieving optimum step coverage, density, and morphology in high aspect ratio trenches and vias presents a significant challenge for PVD technology. Moreover, the eventual use of lower density low-k dielectrics in memory devices will place additional constraints on the pre-clean and sputtering process because physical damage to the dielectric must be minimized. To meet these goals, a new PVD barrier technology (INOVA HCM IONX) has been developed, which allows PVD extendibility to the 3X nm technology node and beyond.

HCM IONX technology leverages the hollow cathode magnetron (HCM) high-density plasma deposition and resputter concepts but incorporates additional features such as an ion extractor to enable improved control of ion energy and density in the deposition and resputter processes, and an atomic layer profiling (ALP) capability that offers improved step coverage while reducing overhang and damage to low-k dielectrics. The enhanced control of ion bombardment provided by the new PVD technology allows further optimization of barrier step coverage, density and morphology in high aspect ratio trenches and vias, thereby enabling the thinner barriers required for continued scaling. Figure 1a illustrates the enhanced TaN step coverage and film density that can be achieved with the process. This process has also been applied to alternative Ti-based barriers, which offer the potential to provide both lower cost and higher EM reliability [1].


Figure 1. SEM photos showing a) near-conformal high density Ta(N) barrier deposited in a dual damascene trench/via structure; and b) near-conformal copper seed deposited into a high-aspect ratio trench.
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This new barrier deposition process can also be applied to deposition of the copper seed, enabling better control of copper seed step coverage and profile. Seed profile control is particularly important at the opening of high-aspect ratio features, since film protrusion or overhang can lead to voids in the subsequent copper ECD process. Likewise, continuous and adherent seed coverage along the sidewalls is essential to providing a firm foundation for the ECD copper, as any discontinuities in the seed layer provide void nucleation sites that can lead to subsequent VSM- or EM-induced failures. Figure 1b illustrates the copper seed profile control enabled by the new PVD barrier technology process, which greatly facilitates the subsequent copper ECD process.

While a thinner, more conformal copper seed aids the ECD filling process, the higher resistance of thinner seed layers does present a significant challenge to plating uniformity due to the voltage drop across the high resistance film between the contacted edge of the wafer and the wafer center. This voltage drop is commonly referred to as the “terminal effect.” The terminal effect leads to a drop in the plating current near the center of the wafer, which results in reduced Cu thickness compared with the wafer edge. Unless there is compensation for the variation in plating current, the plated thickness will be thicker at the wafer’s edge than at its center.

In response to the challenge of plating on thinner copper seed layers, two novel hardware solutions for improved plating uniformity have been implemented on the SABRE Extreme Electrofill tool. First, compensation for the terminal effect induced by a high resistance seed layer is achieved by insertion of a high resistance virtual anode (HRVA) between wafer and anode. Because the resistance of the virtual anode in the circuit is much larger than the resistance of even very thin copper seed layers, the virtual anode acts to minimize the impact of voltage drops across the seed layer and allows a uniform plating current independent of incoming seed layer resistances. Further control of Cu thickness near the wafer’s edge is realized by modulation of current from the very edge of the wafer by using proprietary dual cathode technology. This additional control over plating current enables tuning of the thickness profile at the wafer edge for compatibility with subsequent chemical mechanical planarization (CMP) processes, e.g., edge thick, flat or thin. Low down-force electrical contacts have also been implemented to accommodate thin copper seeds.

While achieving good plating uniformity is important to facilitate subsequent CMP processing, it is even more critical to achieve void-free copper fill, since voids represent a fundamental yield and reliability issue. Meeting this challenge has required both hardware and process optimization. For example, bottom-up fill of the smallest features will occur within a few seconds at the 3X nm technology node. This accelerated fill has necessitated hardware innovations to enable optimized wafer immersion and precise control of all entry conditions including rotation, entry speed and especially the timing and profile of the electrical waveform applied to the wafer holder assembly. For example, accurate control of the electrical profile is achieved by using a potentiostat connected to a reference electrode to ensure constant current density during the initial stages of plating. Additionally, a uniform fill process also requires a judicious choice of accelerator, suppressor and leveler components in the electroplating bath [2].


Figure 2. Copper Electrofill of 3x nm trenches with minimum feature size of 36nm and aspect ratio of 5:1.
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Both the suppressor and leveler components effectively inhibit plating current in the field regions, thereby reducing overgrowth after filling to provide a more planar surface for the subsequent CMP planarization. Advanced chemistries such as Viaform Extreme Plus or Rohm & Haas UF3001 have been optimized to achieve the accelerated fill required for the 3X nm node and beyond while still maintaining a high degree of surface planarity. The high density trench structures shown in Fig. 2 illustrate the fill capability of advanced plating chemistries developed for the 3X nm memory node.

Co-optimization of ECD and subsequent CMP continues to play an important role in minimizing post-CMP defects for robust interconnect reliability and in achieving uniform and repeatable planarization. Because planarization of the copper damascene trench directly impacts both resistance and capacitance, maintaining precise and repeatable control of dishing and erosion across the wafer is crucial to device yield, performance and reliability. In response to this challenge, a polishing technique has been developed that utilizes closed loop control of multi-zone carrier pressure combined with real time thickness measurement to enable insitu optimization of the copper thickness profile across the wafer [3].

The results shown in Fig. 3a highlight the improved control of post-CMP thickness enabled by the CuVision closed-loop polish profile optimization system as compared with conventional fixed pressure polish. The fixed pressure polish resulted in a high post standard deviation, which would result in uneven copper clearing and a large within wafer dishing range. On the other hand, the closed loop control system adjusted the pressures to minimize copper thickness non-uniformity, resulting in uniform copper clearing and a lower within wafer dishing range that meets the requirements of 3x nm memory technology.


Figure 3. a) Comparison of thickness control for fixed polish pressure vs. CuVision closed-loop polish profile optimization system; b) Orbital CMP with “through-the-pad” delivery system and comparison of consumable costs with conventional rotational CMP.
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With continued pricing pressures on memory products, manufacturers must take steps to reduce process costs to realize the advantages of integrating Cu into their technology. CMP consumable costs often account for >70% of the total cost per wafer pass in Cu CMP, offering the greatest opportunity for cost reduction. On the Xceda xT, CMP cost reductions are achieved through the use of a “through-the-pad” slurry delivery system that delivers slurry directly to the wafer surface, effectively eliminating slurry waste found on conventional rotary systems. This approach reduces the cost of consumables by >25% (Fig. 3b).

Another process that is key to copper interconnect reliability is deposition of the dielectric barrier that caps the top of the damascene structure and prevents copper out-diffusion. From an EM reliability standpoint, the interface between the dielectric barrier and the copper interconnect is possibly the weakest link in the overall copper damascene structure. Thus, optimization of this interface has been the focus of much recent work, both to improve adhesion between the dielectric barrier and underlying copper and also to passivate the copper surface.


Figure 4. a) Schematic of PSAB and dielectric barrier deposition process executed on the Vector Express. b) SIMS depth profile of a specially designed Cu on Cu structure illustrating the segregation of Si atoms at the Cu interface and its diffusion into the underlying Cu film after a specific PSAB process.
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While it is well known that pretreatment of the copper surface in hydrogen or ammonia promotes adhesion by reducing residual copper oxide, more recent studies have shown that passivation of the copper surface using a nitrogen quenched interfacial silicon doping can provide further improvement in adhesion as well as interconnect reliability [4]. This PECVD self-aligned barrier (PSAB) process is performed in situ at the first station of the VECTOR PECVD platform, and process conditions such as temperature can be optimized independently of subsequent deposition steps due to the flexibility of separate process control at each VECTOR station (Fig. 4).

Whereas the quality of the dielectric-copper interface is a key contributor to overall interconnect reliability, properties of the overlying dielectric such as breakdown voltage, hermeticity, and elastic modulus, are also important from a performance and reliability standpoint. In general, higher elastic modulus compressive films provide a film with better capping layers for suppression of Cu migration, and denser films, which tend to have a higher breakdown voltage, provide enhanced hermeticity. The memory industry’s stringent dielectric barrier requirements have thus far been met by using a dense high-breakdown silicon nitride film deposited on the VECTOR platform. By leveraging the synergism between the manufacturing-proven SiN film and PSAB pre-treatment processes, co-optimization of both interconnect performance and reliability can be attained.

As in logic technology, the movement to lower dielectric constant materials — both for the dielectric barrier and inter-layer dielectric (ILD) layer — is a new paradigm under consideration. Carbon-doped silicon nitride (SiCN) materials for dielectric barriers and carbon-doped silicon dioxide (CDO) materials as ILD are well understood approaches for achieving the needed interconnect performance through capacitance reduction. However, the materials needed for memory applications need to be optimized not only for their dielectric constant, but also for electrical breakdown and leakage performance because the electric fields experienced in memory applications can be much larger than those found in logic devices. Further, the required mechanical and adhesive properties of these materials are likely to be much greater due to the highly cost-focused nature of the assembly process.


Figure 5. WN/W via to Cu bitline.
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While optimization of the copper damascene structure benefits both logic and memory devices, new reliability issues have been encountered with the introduction of copper for memory bitline. Specifically, the merger of high temperature aluminum reflow via fill processes with the underlying copper bitline has raised a concern over barrier reliability. To circumvent this issue, a new application has emerged whereby a tungsten via plug (Fig. 5) provides the contact between the copper bitline and standard (non-reflow) aluminum interconnect. The ALTUS DirectFill deposition process substitutes a WN liner for the previously used Ti/TiN liner, thereby enabling a unique all tungsten-based plug that provides improved interconnect reliability while also lowering overall process and tool cost [5].

Finally, with respect to device contacts, the predicted implementation of copper continues to be pushed out in time given the steady improvement in tungsten resistivity enabled by processes such as those on the ALTUS platform that enable thinner nucleation layers and larger grain size [6]. It is likely that any future implementation of copper contacts will also require a CVD or ALD barrier, and more development is needed to fully assess the risk vs. reward for insertion of copper contacts at the device level.

As exemplified by the process flow discussed above, a predominant focus for equipment development is to extend tool and process capabilities while simultaneously improving productivity as measured by performance vs. cost. Such sustained emphasis on productivity and technology extendibility is of critical importance as the semiconductor industry continues to develop innovative solutions for an increasingly cost-sensitive consumer-driven end market. And as memory device manufacturers continue their transition to copper interconnects, it is especially important to have innovative manufacturing solutions that help realize aggressive density and performance goals at an affordable cost.

Acknowledgments

Xceda, INOVA, SABRE, Extreme Electrofill, VECTOR, ALTUS are registered trademarks and Vector Express, IONX, HRVA, PSAB, CuVision are trademarks of Novellus Systems Inc. UF3001 is a trademark of Rohm and Haas. ViaForm Extreme Plus is a trademark of Enthone Inc.

References

  1. W. Wu et al, “Ti-based Barrier for Cu Interconnect Applications,” Proc. of the IITC, p. 202, 2008.
  2. J. Reid et al., “Electrofill Challenges and Directions for Future Device Generations,” Proc. of ADMETA 2007, Oct. 22, 2007, The University of Tokyo, Tokyo, Japan.
  3. B. Brown, “Closed-Loop Control for Improved Cu CMP Technology,” Proc. of the SEMI Tech. Symp., Korea (2007).
  4. K. Chattopadhyay et al., “In situ Formation of a Copper Silicide Cap for TDDB and Electromigration Improvement,” Proc. of the Inter. Reliability & Physics Symp., p. 128, 2006.
  5. J. Collins et al, “Tungsten Nitride Barrier/Tungsten Via to Copper Interconnect for Memory Device Applications,” Proc. of the Adv. Metallization Conf., p. 35, 2008.
  6. A. Chandrashekar et al, “Reducing Effective Tungsten Line Resistivity with Advanced Pulsed Nucleation Layer,” Proc. of the Adv. Metallization Conf., p. 141, 2008.

Robert H. Havemann received his BA and MS in electrical engineering from Rice U. and his PhD in electrical engineering from the U. of Colorado and is VP of External Research at Novellus Systems, Inc., 4000 North First Street, San Jose, CA 95134 USA; 408-943-9700; email bob.havemann@novellus.com.

G. Andrew Antonelli received his BS in physics from Davidson College and his MS and PhD in physics from Brown U. and is technology development manager for the Advanced Dielectrics Group at Novellus Systems, Inc.

Greg K. Arendt received his BS in chemical engineering from Northwestern U. and is senior manager for business development and operations for the CMP Business Unit at Novellus Systems, Inc.

Michal Danek received his BS and MS in chemistry from Charles U. in Prague and his PhD in chemistry from the Massachusetts Institute of Technology, and is senior director of technology for the Direct Metals Business Unit at Novellus Systems, Inc.

Andrew J. McKerrow received his BSc and PhD in chemistry from Queen’s U. in Canada and is director of technology for the Electrofill Business Unit at Novellus Systems, Inc.

Richard S. Weinberg, received his BS in mechanical engineering from Rensselaer Polytechnic Institute and his MS in mechanical engineering from Stanford U. and is director of product management for the Integrated Metals Business Unit at Novellus Systems, Inc.