Issue



The reliability margin of interconnects for advanced memory technologies


05/01/2009







G. Beyer, S. Demuynck, M. Stucchi, I. Ciofi, Zs. Tökei, IMEC, Leuven, Belgium

The trends of decreasing dimensions and new materials motivated the investigation of how these may affect the dielectric reliability of the interconnect structures. We posit that for a given supply voltage, the electrical field increases not only by the shrinking half-pitch, but also by the line edge roughness (LER) and the misalignment of vias.

With the continuing aggressive scaling of dimensions and introduction of new materials, the dielectric reliability margin of interconnects in DRAM and Flash memory chips needs to be re-assessed. Line edge roughness and misalignment of vias increase the electrical field between metal wires.

As the half pitch (hp) of the interconnect structures decreases, both the line edge roughness and misalignment of vias need to be reduced. The replacement of tungsten by copper in damascene wires may lead to a loss of lifetime, if residues on top of the dielectric spacing are not well controlled. The lowering of the dielectric constant from 4.2 (silicon oxide) to 3.0 (carbon-doped oxide) does not, however, appear to impact the dielectric lifetime of damascene structures with a dielectric spacing of 40???50nm width.

LER and misaligned vias

Memory-intensive system-on-chip (SoC) applications such as mobile phones and multimedia require shrinking the dimension of storage devices and interconnects for dynamic random access memory (DRAM) and Flash. This trend is predicted to continue in the future by the ITRS roadmap [1], e.g., in DRAM (Table 1). The choice of interconnect materials has been very traditional with polysilicon, tungsten, aluminum, and silicon oxide dominating the interconnect structures of DRAM and Flash, as opposed to the logic interconnect technology. The ITRS roadmap, however, predicts more widespread use of copper and dielectrics with a permittivity lower than the one of silicon oxide.


Table 1. Scaling trend for DRAM interconnect half-pitch and inter level dielectric constant as predicted by the ITRS roadmap (2007 update) [1].
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LER originates from the patterning processes of transistor gates and wires; it consists of an irregular side profile of the patterned poly or metal lines, featuring protrusions and notches with nanometer range amplitude. LER has been studied and modeled to evaluate its impact on the electrical performance of deep submicron transistors [2] and on the line resistance [3,4].


Figure 1. a) Local reduction of wire spacing generated by LER; b) by misaligned vias. Impact of line edge roughness.
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Misaligned vias in interconnects are due to alignment limitations in patterning steps. Both LER and misaligned vias are responsible for a local reduction of the spacing between wires (Fig. 1), which in turn enhances the electric field locally and represents a weak point for dielectric reliability. The amplitude of neither LER nor misaligned vias scales with shrinking wire dimensions. Therefore, their relative impact becomes more pronounced in future technology nodes, especially for memories where the dimension scaling is of primary importance for increasing storage capacity.

The electric field enhancement induced by LER occurs when two protrusions of adjacent wires are facing each other (see the circles in Fig. 1a). The worst case occurs if these two protrusions have maximum amplitude. The distribution of the protrusions and notches along the wire length is statistical; intuitively, the probability to get protrusions of given amplitude facing each other in two adjacent wires increases with the wire length.


Figure 2. Probability of LER field enhancement vs. wirelength for 30nm-spaced wires, 1V (Enom=0.33MV/cm), 3σLER=7.4nm and λ=42nm.
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This hypothesis can be confirmed by using the statistical 2D LER model on interconnects developed to quantify the probability of occurrence with wire length of a certain local LER field enhancement [5]. This is done by generating the stochastic LER sequence on two adjacent wires 100 times for each wire length, ranging from 10???50??m, and by tracking the occurrence of each value of the local field enhancement. The model is calibrated with realistic values of LER parameters as amplitude 3σLER and correlation length (λ). The 3D plot in Fig. 2 shows the results of this experiment.

The enhanced field is substantially higher than the nominal field Enom in absence of LER, and each enhanced value becomes certain (probability =1) at least in one location beyond a critical wire length. For instance, for the LER values given here, there is a high probability that an interconnect segment with a length of ~25??m will need to support an electrical field that is ~1.5?? higher than the nominal field due to LER.


Figure 3. Non-uniform electric field of 2 LER protrusions facing each other. Values of the maximum non-uniform field ELER_max, values of the field due to LER space reduction ELER_nom, and value of the field without LER Enom are also indicated.
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In addition to the local space reduction between wires, LER protrusions accumulate electric charge at their tips, thus further enhancing the electric field. To take this effect into account, a more detailed analysis of the local field enhancement generated by LER is performed by a static solver (Raphael by Synopsis) [6]. Two LER protrusions, with realistic amplitude (5nm), width (20nm) and curvature of the tip (r =4nm) generate a local non-uniform electric field between the wires, as illustrated in Fig. 3.

The maximum magnitude ELER_max of the LER-enhanced field is located at the proximity of the tip and is higher than the field ELER_nom estimated by assuming a local reduction of the wire spacing due to LER; both these enhanced fields are substantially higher than the nominal field. Simulations with different curvatures of the LER tip suggest a generic correction factor of 1.5 for adding the charge accumulation effect to the local space reduction, as adopted in the red scale in Fig. 2. For the specific wire geometry and LER considered in the figure, the local field increases by ~40%.

In summary, we have proposed two mechanisms that increase the electrical field: decrease of dielectric spacing due to protrusions; and field enhancement at the tip of a protrusion.

Since LER is inherent to patterning, the magnitude of it can be modulated by the choice of patterning technology. For instance, it is possible to auto-correlate the LER on both sides of wires facing each other, such that there is no decrease of the dielectric spacing. This is achieved by spacer-defined patterning, currently adopted in sub-50nm wire spacings. In this technology, a protrusion into the dielectric spacing corresponds to a projection of the dielectric into the wire at the opposite side, virtually eliminating any local space reduction between wires. In this case, the field enhancement effect by LER is only due to the charge accumulation effect on the tip of the LER protrusion. Therefore, we can conclude that LER becomes an important contributor to the dielectric reliability of sub-50nm dielectric spacings due to the field enhancement by a factor of ~1.5.

Impact of misalignment of vias

Depending on the patterning approach and the capabilities of the lithography tool, the position of the via with respect to the connecting wires may be shifted in the in-plane directions. What is more, the design requirement of zero overlap between wires and vias makes alignment of the via to the wires even more critical. The misalignment steps act as field-enhancing protrusions (Fig. 1b), and their impact on the field can be evaluated by 3D Raphael simulations.

The maximum field is non-uniform and localized at the corners of the steps generated by via-metal misalignment. The magnitude depends on the voltage between the lines and on the severity of misaligned vias. For a wire spacing of 30nm, a misalignment of 5nm causes a local 50% increase in the field with respect to Enom; a 10nm misalignment causes more than a 100% local increase.

LER and misaligned vias coexist in wires and the consequent field enhancement is not negligible in narrow lines. For short lines (~10??m) with vias, the impact of LER becomes probabilistic; in other words, the shorter the line, the more likely that the impact of misaligned vias is predominant. On the other hand, long lines (>10??m) will have the contribution of both misaligned vias and the full LER contributions to field enhancement; one of these effects will be predominant according to the relative contribution of these two field enhancement factors in different scaling scenarios [7].

Impact of materials choices on reliability margin

To evaluate the influence of LER and materials choices on the dielectric reliability, single damascene structures with narrow dielectric spacing of ~50nm were created by double patterning [8]. With this method, it is possible to halve the pitch of damascene structures with the same lithography tool. This approach is considered as essential to produce interconnect structures for advanced memory applications. Figure 4 shows transmission electron microscope (TEM) cross-sections of the structures investigated: on the left there is an example of a narrow oxide spacing separating two trenches that are filled with tungsten. In the center cross-section, the tungsten has been replaced by copper. On the right, 50nm hp structures are displayed consisting of copper trenches embedded in a carbon doped oxide with a k-value of 3.0.


Figure 4. Transmission electron microscope (TEM) cross-sections of the investigated single damascene structures: tungsten/oxide (left), copper/oxide (center), and copper/carbon doped oxide. The width of the dielectric spacing is ~50nm.
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The manufacturing of small-pitch structures requires extensive modeling of the lithography and etch processes, resulting in an optical proximity correction of the test structures. Critical parts of the interconnect structure are corners, turns, line ends, and variations in the pitch such as on the periphery of the structure, which usually result in deviations of the hp design rules such as narrowing of the dielectric spacing and widening of the copper line, and vice versa. Consequently, these parts of the damascene structures may be particularly vulnerable to dielectric or electromigration reliability failures.


Figure 5. Breakdown field evaluated on a k=3.0 CDO low-k material spacing of ~47nm for structures with the same line length but variations in layout, comparing parallel lines to fork-fork and meander-fork structures with differences in the amount of meander turnings in the design.
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To chart the impact of the structure layout on dielectric reliability, the breakdown field was recorded on parallel lines, meander-fork structures with different amounts of turns in the meander and in fork-fork structures [9]. The length of the structures that were stressed was the same (1cm). As shown in Fig. 5, the layout of the damascene structures has considerable impact on the electrical field that the structure can support. Parallel lines and fork-fork structures, which essentially consist of straight lines, have the highest breakdown strength. When corners and turns are inserted, the breakdown field strength decreases by 1-1.5MV/cm.


Figure 6. Breakdown field evaluated on a k=3.0 CDO low-k material or SiO2 spacing as a function of line length on a parallel-line test structure. The estimated spacing on the low-k test structures is ~47nm and ~40nm for the SiO2 test structures.
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Turns and corners in a copper line are deliberately inserted during the interconnect test structure design to increase the length of the wires and, if the layout rules permit, can be avoided. LER is, however, inherently related to a specific patterning process and occurs randomly on a much shorter length scale. Therefore, parallel lines were chosen to study the effect of LER as this design allows varying the length of the interconnect structure over several orders of magnitude. This is illustrated in Fig. 6 in which the breakdown field strength of narrow dielectric spacings, consisting of either oxide or a non-porous carbon doped oxide k=3.0 materials, are compared. The impact of the LER is reflected in an initially faster decrease of the breakdown field as a function of structure length for both materials. This is entirely consistent with Fig. 2, which predicts that the LER-induced field enhancement is less pronounced for short lines (<10???20µm). In practice, this also implies that on longer lines one observes ~1MV/cm lowering in the breakdown strength induced by LER combined with regular area scaling. Interestingly, the breakdown strength of the carbon-doped oxide and the oxide are similar.


Figure 7. Constant voltage TDDB tests for copper/low-k, copper/SiO2 and tungsten/SiO2 lines. The dielectric spacing was 50nm and the measurements were conducted at 100°C. The length of the interconnect line is given in the legend in µm units for meander-fork (MF) and parallel line (PL) structures.
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Figure 7 compares the various tested interconnect materials in the form of a time dependent dielectric breakdown (TDDB) plot. It is not unusual to observe that tungsten metallization outperforms copper, i.e., at a given field, the breakdown occurs faster for copper lines. In the case of damascene oxide lines, the weakest interface is the top CMP interface. In general, any defect (scratches, particles, slurry residue, corrosion, etc.) at that interface will lead to early degradation regardless of the metal used. In particular, for copper it was recognized early [10, 11] that residual copper on the CMP interface leads to additional lowering of the breakdown field. A quantitative relation between the amount of copper residues and breakdown was recently established [12]. From those studies one can conclude that in order to have noticeable degradation induced by copper metallization the threshold lies at ~1012 Cu atoms/cm2 between the copper lines. To mitigate the impact of copper, besides appropriate top-surface plasma treatments and dielectric-cap diffusion barrier selection, one needs to ensure that the amount of residual copper is lowered below that threshold.

Introducing a low-k material together with copper metallization could potentially also influence the reliability margin. Therefore, in Fig. 7, we have also plotted the observed TDDB behavior of 50nm hp copper low-k interconnects. The data was collected on longer and layout-sensitive meander-fork structures in order to illustrate the impact of the layout-induced field enhancement. Indeed, as expected from Fig. 5, this results in a lowered breakdown field, which is ~0.8MV/cm less than the shorter straight Cu/SiO2 parallel lines.

Memory applications

In general, interconnect dielectric reliability is not a concern for memory applications as long as silicon dioxide is used in combination with a sufficiently relaxed dielectric spacing. However, starting at ~50nm dielectric spacing and certainly below, concerns do exist [13-15]. Of course, using a TDDB plot as presented in Fig. 7 for assessing inter-metal dielectric reliability of memories is an oversimplification. Nonetheless, these plots can provide a worst-case estimate and a first assessment of TDDB at a given field; assuming a continuous stressing, the predicted lifetime can be read out at any constant field value. For example, for the copper low-k combination this means that a 10-year lifetime can be achieved at a 1.4MV/cm of continuous stress; one year can be guaranteed at 2MV/cm of continuous stress, and a one-month lifetime at a field of ~2.2MV/cm. For a more accurate assessment, one should take into account how frequently the considered interconnect is used, how many times the memory cell is programmed, how often it is read-out, what is the width of the observed breakdown distributions, etc.

However, that goes beyond the scope of this short discussion. Nevertheless, the above data clearly illustrates that the investigated k=3.0 low-k material, as well as the SiO2 structures, have the potential to be integrated with copper as conductor into memory interconnects that reach the necessary reliability specifications with spacing values of 50nm and beyond.

Conclusion

The impact of material choice and structure geometry on interconnect dielectric breakdown was discussed in the context of memory applications. The presence of line edge roughness can lead to a local field enhancement as high as ~1.5?? the nominal field value beyond a critical length of ~10µm, which in turn results in early breakdown. It is very important to minimize LER.

Besides LER, via misalignment needs to be minimized and in the layout itself one has to avoid any unnecessary irregularity, where the dielectric field would be enhanced in tight pitch interconnects. When comparing copper and tungsten metallization, it is clear that copper can degrade the dielectric reliability if the amount of copper residues after CMP is >1012at/cm2. The introduction of a CDO k=3.0 low-k material does not lead to significant degradation as compared to deposited silicon dioxide. A 10-year lifetime is demonstrated at a constant field of 1.4MV/cm. These data are very encouraging for being able to accommodate high operating voltages in memory-based copper low-k circuits.

Acknowledgments

The contribution of the Cu/low-k program at IMEC is acknowledged. Particular thanks are accorded to Rama Alapati (Micron assignee at IMEC) and Els Parton (IMEC) for their help with the manuscript. Aurora is a registered trademark of ASM.

References

  1. ITRS roadmap, 2007 edition.
  2. J.A. Croon et al., “Experimental Investigation of the Impact of Line-edge Roughness on MOSFET Performance and Yield,” Proc. of ESSDERC 2003, pp. 227-230.
  3. L.H.A. Leunissen, W. Zhang, W. Wu, S.H. Brongersma, “Impact of Line-edge Roughness on Copper Interconnects,” Jour. of Vac. Science Tech., B, Vol.24, n.4, July/Aug. 2006.
  4. M. Stucchi, M. Bamal, K. Maex, “Impact of Line-edge Roughness on Resistance and Capacitance of Scaled Interconnects,” Microel. Eng., Vol. 8, Issue 11, Nov. 2007, pp. 2733-2737.
  5. F. Chen et al., “A Comprehensive Study of low-k SiOCH TDDB Phenomena and Its Reliability Lifetime Model Development,” IEEE IRPS, San Jose, CA, 2006, pp. 46-53.
  6. Synopsis Raphael Reference Manual, 2006.03.
  7. M. Stucchi, Z. Tokei, “Impact of LER and Misaligned Vias on the Electric Field in Nanometer-scale Wires,” Proc. of the IITC, 2008, p.174.
  8. G. Beyer et al., “CMOS 32nm Technology Node: Business as Usual for Interconnect Damascene Patterning?” Semiconductor Fabtech, Vol. 38, 2008, pp.70-77.
  9. S. Demuynck et al., “Dielectric Reliability of 50nm Half-pitch Structures in Aurora LK,” Proc. Inter. Conf. on Solid State Devices and Materials, 2008, p.722.
  10. J. Noguchi, N. Ohashi, J. Yasuda, T. Jimbo, H. Yamaguchi, N. Owada, et al., “TDDB Improvement in Copper Metallization under Bias Stress,” Proc. IEEE IRPS, San Jose, CA, 2000, pp. 339-343.
  11. J. Noguchi “Dominant Factors in TDDB Degradation of Copper Interconnects,” IEEE Transactions on Electron Devices, vol. 52, pp. 1743-1750, 2005.
  12. N. Heylen et al., Proc. Adv. Metallization Conf. (AMC), (2008), in print.
  13. S.W. Lee, G.H. Choi, S.T. Kim, U. Chung, J. T. Moon “Metallization in Memory Device: Present and Future,” Proc. IEEE IITC 2006, San Francisco, CA, pp.69-71.
  14. H.B. Lee, J.W. Hong, G.J. Seong, J.M. Lee, H. Park, J.M. Baek, et al., “A Highly Reliable Cu Interconnect Technology for Memory Device,” Proc. IEEE IITC 2007, San Francisco, CA, pp. 64-66.
  15. H. Park, H.B. Lee, H.K. Jung, Z.S. Choi, J.Y. Bae, J.W. Hong, et al., “Voltage Ramp and Time-dependent Dielectric Breakdown in Ultra-narrow Cu/SiO2 Interconnects,” Proc. IEEE IITC 2008, San Francisco, CA, pp. 49-51.

Gerald Beyer, PhD, is the manager of the Cu/low-k program at IMEC, Kapeldreef 75, 3001 Leuven, Belgium; ph. 0032-16281894; beyer@imec.be; www.imec.be.