Identifying yield-impacting polishing-induced defects on polished silicon substrates


H. Suh, K. Kim, S. Venkat, W. Shen, J. Park, I. Seo, KLA-Tencor Corp., Milpitas, CA USA and B. Moon, J. Kim, S. Lee, Y. Shin, J. An, J. Ku, S. Park, Hynix Semiconductor, Icheon-si, Korea

Traditional incoming wafer quality analysis methods have proven inadequate in detecting polishing induced defects (PID). A new nondestructive methodology that enables defect capture and reliably distinguishes between these device-killing defects and innocuous cleanable particles has been developed.

A new class of yield-impacting defect types, PIDs, on polished silicon substrates have been found to cause significant yield drop associated with a failure in the sub-60nm flash memory process. While SEM and AFM methods were able to verify the defect issue as PID in the fab, neither of these techniques is production-worthy for routine inspection of incoming wafers. The problem had also not been detected during outgoing wafer quality analysis at the wafer manufacturing plant.

This study utilized KLA-Tencor’s SP2XP unpatterned wafer inspection system, a tool that combines multiple illumination angles and multiple detectors with a rule-based binning (RBB) algorithm for defect detection and classification. Three rules were developed to improve the classification of PID vs. particles. All three were based on comparing the ratio of scattering signals between detectors or combinations of detectors.

Defect detection/classification

With the constant drive to attain ever smaller critical dimensions in IC device manufacturing, the critical defect size that will impact yield and performance also shrinks, as captured in the ITRS roadmap [1]. On the strength of this data, it can be inferred that timely detection and classification of defects assumes greater significance. With the march of progress, besides conventional defect types that have been studied earlier, new defect types hitherto of no concern also emerge, necessitating newer techniques and methodologies of detection and classification.

The conventional defect types commonly encountered in semiconductor manufacturing include extrinsic defects such as particles, crystal defects such as crystal originated pits (COP), and process-related defects such as residues. These defects are detected and classified by the existing detection recipes and methodologies.

With the continuous shrinking of device sizes, newer defect types are emerging that were previously not critical for device yield. These new defect types evade detection by conventional methods that are in place. The defect type discussed here is polishing induced defects.

PID yield impact at sub-60nm flash memory

A case of yield loss was observed on a particular wafer group in flash memory processing. Upon troubleshooting, these wafers were found to be causing a bias failure. The program voltage was found to be shifted. Flash memory performance is known to be more sensitive to wafer surface quality than other devices. The failure was leading to a significant yield drop, partly because the conventional wafer quality methods could not differentiate between the good and bad wafer groups. The conventional methods used at wafer manufacturers include:

  • gate oxide integrity (GOI) analysis
  • near surface micro defect (NSMD) analysis
  • LPD outgoing inspection@50nm
  • Flatness
  • Nanotopography.

The conventional wafer quality monitor methods used at IC manufacturers include:

  • Metal contamination analysis
  • Organic contamination analysis
  • Device fail rate vs. LPD count analysis@50nm.

Incoming wafer monitor at 37nm on an SP2

However, further investigation with SP2 at 37nm threshold showed high defect counts on the problem wafer group during specific periods and the major defect type was identified as PID. SEM and AFM analyses revealed this defect type as being shallow and flat. At the same time, lot history investigation for the problem wafer group showed this defect type was highly related to the polishing process.

Non-cleanable nature of PIDs

Additional characterization study was carried out to understand the nature of these defects causing the yield loss with cleaning process. The wafers with PIDs were cleaned in an attempt to remove these defects. The PIDs were found to be non-cleanable and also, the cleaning process did not change their shape. This was confirmed by defect analysis using pre- and post-SEM review. This result sets them apart from particles that are removed by cleaning process. Figure 1 summarizes the results of the cleaning process.

Figure 1. Cleanable particles vs. non-cleanable PIDs.
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Having established that the PIDs are yield-killing defects, it is important to classify them accurately and promptly. With the conventional methods available proving to be inadequate, a new methodology must identify PIDs. Because these defects are new and are difficult to monitor due to limited detection at the 50nm threshold, the requirements of the new methodology, besides better sensitivity, would be to collect as much defect information based on their scattering characteristics.

To achieve this goal, the SP2XP system was used. Two incidence modes oblique/normal and two collection channels wide and narrow with a UV source were employed. The wafer inspection system works by rapidly scanning a laser spot in a spiral pattern across the surface of the wafer. Scattered light is collected in large solid-angle collectors, which integrate the signal to detect small defects. Because the shape, size, and material of the defect and the wafer substrate affect the way the defect scatters light, normal and oblique incidence angles, narrow and wide collection channels, and selectable polarizations provide flexibility to capture all defect types. This system also enables dual scans and flexible defect classification rules created with rule-based binning (RBB).

The advantage is fully utilizing the light-scattering intensity information of different polar angles according to the defect types with RBB rules. Each defect type exhibits a unique scattering profile, which allows classification of defects by type.

RBB classification methodology and results

Defect characterization studies were carried out in dual incidence mode. Defects will have size information from four dark field (DF) channels, overlaid to create a grand composite. Typically, a particle will be reported with the same size across all the four channels. If a size ratio were to be calculated, it would be close to or equal to one. However, as mentioned earlier, PIDs have different scattering polar angles than particles, thereby giving rise to a different size ratio from particles. RBB rules that made use of this difference were developed to separate the non cleanable PIDs from the cleanable LPDs. A set of twelve 300mm prime polished wafers was used for this study, which had a total defect count of 3125. For this study, the four DF channels will be labeled as A, B, C, and D.

Figure 2. Rule 1 defect separation ratio.
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Rule 1. This rule applies only to those defects that were common between channels B and C. The sizes of the defects common to these channels were compared. Figure 2 shows the plot of defect sizing between channels B and C. At a sizing ratio of 1.45, PIDs are clearly distinguishable from particles and other fall-ons. Those defects that fall below this ratio were LPDs, while the ones above this ratio were found to be PIDs. This was confirmed by the cleaning test. This rule covered 774 defects, about 25% of the total. High levels of purity and accuracy for separation was observed, as illustrated in Table 1.

Table 1. Purity and accuracy results for Rule 1.
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Rule 2. This rule applies only to those defects that were common between channels A and B. The sizes of the defects common to these channels were plotted against each other and the ratio at which there was good separation was determined to be 1.25 as shown in Fig. 3. Those defects that fall below this ratio were LPDs, while the ones above this ratio were found to be PIDs. This was confirmed by the cleaning test. This rule covered 310 defects, about 10% of the total number of defects. Although this covered fewer defects than rule 1, higher levels of purity and accuracy for separation were observed (Table 2).

Figure 3. Rule 2 defect separation ratio.
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Table 2. Accuracy and purity results for Rule 2.
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Rule 3. This rule was developed based on the preferential scattering properties of PIDs into specific channels on the measurement tools. In scatter studies, it was observed that PID scatter intensity was the maximum in the B and D DF channels relative to channels A and C. This rule applies to all defects that were captured in those two channels. The defect count analysis was performed between removed and remaining defects after cleaning for the two sets of channels — A and C against B and D as shown in Fig. 4. The rule classifies all defects detected in channels B and D as PIDs. This covered 2039 defects, ~65% of the total defects. The higher defect coverage comes at a slight reduction in the purity and accuracy levels relative to the other two rules (Table 4).

Table 3. Accuracy and purity results for Rule 3.
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Figure 4. Rule 3: Defect count analysis of removed vs. remained defects.
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Table 4. Cumulative classification results and rule descriptions.
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These three rules can be applied either individually or in combination with varying levels of purity and defect coverage. Applying rules 1 or 2 can achieve >90% purity in PID classification while covering up to 35% of the defects. This can be a suitable option for process monitoring. On the other hand, applying all three rules simultaneously can achieve 81% purity in PID classification with 100% defect coverage. This can be effectively applied for device yield monitoring.


A new methodology that makes use of dual incidence inspection and RBB is implemented to effectively detect and classify PIDs and LPDs on polished silicon wafers. Three rules have been developed that make use of scatter characteristics of PIDs to effectively help separate them from LPDs. PID defect monitoring with either Rule 1 or 2 achieves 90% in purity with 35% coverage of total defect count. They are recommended for process monitoring of PID defects for wafer manufacturers. Device yield issue monitoring by total PID defect count control with all three RBB rules achieves purities of 81% in PID and 77% in particle defects, respectively, for all defects and is recommended for IC houses.


The authors would like to thank engineering and applications staff at Hynix Semiconductor Wafer Engineering, Incoming Quality Control Group, and KLA-Tencor’s Surfscan division for contributing.


  1. International Technology Roadmap for Semiconductors,” 2005 Edition, Yield Enhancement, pp. 7-10.
  2. K. Kapkin, C.G Koh, “A New Approach to identify Large Yield Impacting Defects for Polished Si Wafer,” SEMICON Korea STS, p. 163 (2007).

Hyosik Suh can be reached at KLA-Tencor Corp., 1 Technology Drive, MS 3-2040, Milpitas, CA 95035, USA; phone 408-875-7363; email

Byeongsam Moon can be reached at Hynix Semiconductor Inc., Research & Development Division, San 136-1, Ami-ri, Bubal-eub, Icheon-si, Kyoungki-do, 467-701, Korea;