Issue



CMP grows a paunch


04/01/2009







 

Michael A. Fury,
Techcet Group LLC, Del Mar, CA USA

 

There’s no question about it. CMP is showing all the signs of middle age as it ambles past its quarter century milestone. Its rampant growth has decayed to match that of other semiconductor process materials sectors (Techcet Group 2008 CMP Consumables Report).

As CMP settles in as a critically enabling process step, emphasis has shifTed decisively to reducing CMP’s cost of ownership. CMP has displaced lithography as the single most costly unit operation per wafer pass (photoresist accounts for 9% and CMP for 11% of front end material costs excluding silicon according to a Techcet Group 2008 estimate), led by slurry prices that are needed to support the R&D behind these highly tuned materials.

Today’s CMP technology is used in many more process applications than originally conceived. Post-CMP cleaning has become increasingly critical at successively smaller device nodes. The demand for improved performance specifications for CMP technology has several origins:

  • A single digit percentage of performance improvement can bring large financial rewards;
  • Improving flatness using CMP across the chip can provide relief elsewhere in the fab in the form of a larger process window for lithography;
  • Fab production schedules cannot tolerate the CMP sector being down for consumable issues;
  • Maximize the number of good chips per wafer by, among other things, eliminating edge losses (i.e., decreasing the CMP edge exclusion distance);
  • Assure that minimal defects on each process level maximize overall yield;
  • Decrease cost at the point of purchase (managing reduced slurry volumes on top of commodity pricing pressure compounds the strain on suppliers).

 

The net result is that each year, expectations increase for CMP improvements in the areas of yield — edge exclusion, non-uniformity, defectivity — and cost — higher polish rates, longer pad life.

The historical process split between logic and DRAM has now added a third distinct segment, flash memory, which drives enough process and materials differences to warrant identification as a separate process specification. According to the SIA Fall 2008 forecast, flash revenue is already half that of DRAM. Even in an environment that is driven by microprocessors with interconnect levels in the double digits, only the most cavalier supplier would choose to ignore this 6% segment of the market.

3D packaging integration tends to slow down the rate of on-chip interconnect innovation by achieving higher circuit density through other means. In particular, it slows down growth in the number of interconnect levels per memory chip, where 3D packaging is most widely used. Through-silicon vias (TSVs) is one emerging area that may create new market opportunities for processes resembling semiconductor Cu CMP.

MEMS offers its own opportunities for the CMP community to excel. Unfortunately, given the manner in which STI CMP is ofTen discounted as less attractive because it is only one wafer pass, the MEMS market overall is ofTen discounted by suppliers as a market for which the upside opportunity does not warrant the R&D investment.

These are the issues that all semiconductor technologies have faced with the onset of middle age. While we are satisfying the ever-changing needs of the CMOS world, how can CMP leverage what it has learned to profit in other markets? Given the adaptability it has shown thus far, I submit that CMP has a better chance than most to make itself comfortable in other manufacturing technologies. I don’t expect to see many red Corvettes in this mid-life crisis.

Michael A. Fury, PhD, is senior technology analyst at Techcet Group, LLC, P.O. Box 29, Del Mar, CA 92014; email mfury@techcet.com.