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Precursors for group IV epitaxy for micro/opto-electronic applications


04/01/2009







Shawn G. Thomas, Matthias Bauer, ASM America, Phoenix, AZ USA; Matthew Stephens, Voltaix LLC, Branchburg, NJ USA; John Kouvetakis, Arizona State U., Tempe, AZ USA

As device engineers are turning to material scientists to provide new materials for enhanced functionality of device platforms, the materials scientists are turning to chemists to provide new chemistries to realize novel functionality within the epitaxial deposition process. Several non-traditional chemical precursors for silicon, carbon-doped Si (Si:C) and germanium deposition are presented that enable the drive to lower thermal budgets for integration within CMOS and DRAM platforms, among other benefits.

As CMOS dimensional scaling has progressed along the Moore’s Law path for the last 40 years, increasing transistor performance year over year has become more difficult. To this extent, new materials have become an integral component for realizing increased transistor drive current. Epitaxial deposition on the silicon substrate has proliferated within MOSFET structures and become a key enabler to increased transistor performance. The selective growth of SiGe films has been utilized in pMOS transistors for source/drain uniaxial strain engineering [1] while the selective growth of silicon has been utilized in DRAM as a method to reduce parasitic resistance.

As integration schemes become more complex with multiple epi layers incorporated into the process flow and small feature sizes become the norm, there is increased pressure to reduce the thermal budget of the epi process and to come up with methods of increasing growth rates (and thus increasing throughput of a given process) under the constraints of low thermal budgets.

In this paper we will discuss several non-traditional chemical precursors for silicon, carbon-doped Si (Si:C) and germanium deposition that enable improved manufacturability through higher growth rates, novel approaches to interface or band-gap engineering, and new deposition temperature regimes commensurate with the drive to lower thermal budgets for integration in CMOS and DRAM platforms. Among the precursors to be discussed are Silcore (trisilane), dichlorodisilane, and digermylmethane. These precursors can be used to realize a wide range of Group IV heteroepitaxial materials that are compatible with a silicon platform.

New epitaxial processes for CMOS applications

As mentioned previously, the growth of epitaxial SiGe within the recessed source/drain regions of p-channel transistors has been used to induce uniaxial strain in transistors since the 90nm CMOS node. The unaxial strain in these p-channel MOSFETs has been continuously increased by increasing the Ge concentration in the epi film. Just as the drive current of the p-channel device can be enhanced via uniaxial stressors, the same approach can be taken for the n-channel device. The current approach for achieving uniaxial strain in n-channel devices is via techniques such as tensile stress liners or strain memorization [2-4]. However, as the gate pitch gets narrower and these stress techniques become less effective, there is a desire to have an epitaxial source/drain stressor for the nMOS that is the complement to the SiGe stressor in the pMOS.

Silicon-carbon (Si:C) is one materials choice for creating a uniaxial tensile stressor via epitaxy in the source/drain region of transistors. The concept of using Si:C is to epitaxially deposit a material with a smaller lattice constant than Si within the recessed source/drain regions of the transistor to induce tensile strain in the adjacent channel region. However, epitaxy of Si:C is much more challenging than SiGe and imposes many more constraints on the process conditions. First, due to the low solubility of carbon in silicon, it is necessary to grow the epitaxial layers at low temperatures (<600°C) to ensure that the carbon atoms occupy substitutional sites. The impact of this low temperature requirement is that the growth rate using traditional silicon precursors (silane, disilane, dichlorosilane) is reduced, requiring longer processing times per wafer. Another impact of the low temperature requirement is the ability to create a selective process since the etch rate of silicon using HCl also decreases with decreasing temperature.

To tackle these challenges from a chemistry perspective, we turned to alternate precursor molecules to provide a solution. In the case of Si:C epi deposition, we developed an approach using Silcore (trisilane) as a key component of the low temperature selective deposition processes. Trisilane (Si3H8) is particularly useful as a low temperature deposition silicon precursor because it more readily forms a reactive intermediate that has a high sticking coefficient and has available a deposition mode that is not limited by the rate of hydrogen desorption from silicon.


Figure 1. Arrhenius plot comparing deposition rates of silane and Silcore. SOURCE: LETI/ASM
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Trisilane decomposes through the elimination of silane (SiH4) and therefore the key reactive decomposition intermediates of Si3H8 that enable high growth rates are: SiH-SiH3, H2Si=SiH2, and SiH2. Shown in Fig. 1 is an Arrhenius plot comparing the deposition rates of silane and Silcore between 450°C and 950°C. As is shown in the plot, the deposition rate using Silcore is greater than 30X higher than silane at 600°C and below for equal amounts of silicon atoms in the reaction chamber. This property of the trisilane molecule enables us to circumvent the limitation of traditional silicon precursor chemistries to develop a novel process for Si:C that enables us to feature extremely high substitutional carbon concentrations (>2.5%C).


Figure 2. X-ray diffraction spectra of SiC epitaxial films grown using Silcore as the silicon source (monomethylsilane as the carbon source); >2.5% substitutional carbon is measured in the films. Inset: Cross-section TEM image of a selective Si:C epitaxial layer grown within the recessed source/drain region of a transistor.
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Figure 2 contains x-ray diffraction spectra of various Si:C films grown using Silcore demonstrating the high level of substitutional carbon in the film (as indicated by the separation between the Si substrate peak and the Si:C epi peak) and the high quality of the layers (as indicated by the observed Pendell??sung fringes from the Si:C peak). Also shown in the inset of Fig. 2 is a cross-section TEM image of a selective Si:C epitaxial layer grown within the recessed source/drain region of a transistor. Further details of the Si:C epitaxial process can be found in [5].

Another approach investigated for the selective deposition of silicon-based heteroepitaxial layers uses a mix of a new deposition precursor, dichlorodisilane (DCDS), and chlorine as the etchant. We chose dichlorodisilane as a candidate based on thermodynamic and practical considerations. The issue with using trisilane and chlorine together in a selective process is that the gas phase reaction can be highly exothermic under certain conditions (Si3H8 + 10Cl2 => 3 SiCl4 + 8 HCl + 833.8 kcal/mol @ 550°C). Our approach uses the more stable DCDS precursor that releases intermediates such as SiH2 which contribute to epitaxial deposition, leaving less reactive species such as SiCl2H2 in the gas phase that have a low rate of reaction with Cl2 (Si2Cl2H4 + 5Cl2 => 2SiCl4 + 4 HCl + 324.6 kcal/mol @ 550°C). In this way, we obtain the deposition advantages of trisilane (high deposition rate, low temperature decomposition) without the drawbacks (exothermicity) of the Cl2/Si3H8 interaction.


Figure 3. Arrhenius plot of the silicon growth rate of DCDS from 700°C down to 450°C under varying pressure conditions.
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The growth rate of DCDS is orders of magnitudes higher than DCS and on the same order as Si3H8. Figure 3 shows the Arrhenius plot for the growth rate of silicon epi using DCDS (flow rate of DCDS = 50mg/min) under various pressure regimes. For comparison, growth rates of the traditional precursor, dichlorosilane, were included for two pressure conditions and two different carrier gases. The DCS flow was carefully matched to have an identical amount of Si atoms going into the reactor as the DCDS curves. As shown in the figure, under reduced pressure growth conditions (i.e. 100T), the growth rate for dichlorodisilane can be 75X ??? 500X higher than DCS at low temperatures (e.g., <600°C). This makes DCDS an attractive precursor for low temperature selective epitaxy of silicon based films.

Epitaxial processes for novel applications

Next, we describe a recent example of a unique CVD route that permits heteroepitaxy of mismatched Ge films directly on Si substrates for potential optoelectronic and photovoltaic applications. This method is based on the design and application of purpose-built molecular precursors targeted to tailor the surface reactions at the growth front [6]. Deposition of Ge is conducted at low temperatures (330???420°C) at 10-5-10-2 Torr, in the absence of gas phase reactions using molecular mixtures of Ge2H6 (diluted with high purity H2) and small amounts of highly reactive (GeH3)2CH2 or GeH3CH3 organometallic additives as described by the reaction scheme shown in Fig. 4. The driving force for this reaction mechanism is the facile elimination of extremely stable CH4 and H2 by-products, consistent with calculated chemisorption energies and surface reactivities. Collectively, our experiments indicate that the additives confer unique pseudo-surfactant behavior which profoundly alters the classic Stranski-Krastanov growth mechanism of epitaxial Ge on highly mismatched Si surfaces.


Figure 4. XTEM micrographs of the Ge films grown directly on Si(100): a) Phase contrast micrograph showing a 2.5mm film thickness with a flat surface; b) Diffraction contrast micrograph of a 0.8mm film showing an atomically smooth surface and absence of penetrating defects; c) High-resolution image of the heteroepitaxial interface showing the location of Lomer defects providing strain relief.
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Using this approach we have produced atomically smooth (AFM RMS ∼0.2nm) and stress-free Ge films with dislocation densities <104 -105 cm-2, two orders of magnitude lower than those attainable from the best competing processes. As shown in Fig. 3, full relaxation in the films is readily achieved via formation of Lomer dislocations confined to the Ge/Si interface and this allows film dimensions approaching bulk values to be achieved on a Si substrate. These defects are found to alleviate the interface strain associated with the pseudomorphic growth and suppress the propagation of dislocation cores throughout the layer as shown in etch-pit density characterizations. The XTEM micrographs in Fig. 4 show two representative layers with thickness up to several microns, which have been grown at high growth rates of 60nm/min. using a 15:1 molar ratio of Ge2H6:(GeH3)2CH2. Raman and high resolution XRD studies of these samples confirm that the materials are virtually stress- and defect-free.

The desirable growth conditions, low dislocations densities and superior film morphology make Ge films grown by this method an ideal platform for the subsequent lattice and bandgap engineering of photonic materials on a silicon substrate. Among the advantages of using the silicon substrate are the large wafers sizes commercially available (e.g., 300mm diameter), low cost, and high mechanical strength compared to III-V substrates (e.g. GaAs, InP). As Ge is lattice-matched to GaAs, once high quality Ge is grown on the Si substrate using an approach similar to that detailed above, it is then possible to grow high quality GaAs on the Ge epi layer. GaAs grown on a Si substrate using a Ge intermediate layer has been demonstrated and provides a platform to realize optoelectronics or very high speed devices (e.g., HBT, HEMTs) on Si [7-8].

Conclusion

Materials engineering is an instrumental tool enabling a range of devices and applications. The adoption of epitaxial processes into new device architectures mandates epitaxial solutions that are low cost (high growth rates, high throughput) and integration friendly (low thermal budget). As Group IV materials engineering (Si, Ge, C) boosts CMOS device performance, it is also opening the door to new markets for Si-based platforms by bridging the gap between electronics and photonics. Using lattice engineering between Si and Ge, it is now possible to realize III-V materials on large-diameter, low-cost Si substrates. The engineered precursors discussed above are just a few examples of the key enablers to realize these complex electronic and optoelectronic systems. It is anticipated that designer precursors will play crucial functionality and manufacturability roles in this renaissance of materials engineering in the semiconductor industry.

Acknowledgments

Collaborators on these projects include Gary Miller, Leonard Greenfield, Ron Bertram, Chantal Arena, Nyles Cody, and Andrew Chizmeshya, with help from the Department of Energy grant DE-FG36-08GO18003 and NSF STTR program. Silcore and Epsilon are registered trademarks of ASM International N.V.

References

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  7. K. Chilukuri et al., “Monolithic CMOS-compatible AlGaInP visible LED arrays on silicon on lattice-engineered substrates (SOLES),” Semicond. Sci. Technol. 22, 2007. p. 29-34.
  8. S.G. Thomas, et al., “Fabrication and Characterization of InGaP/GaAs Heterojunction Bipolar Transistors on Germanium on Insulator (GOI) Substrates,” IEEE Elect. Dev. Lett., vol. 26, no. 7, 2005. p. 438.

    Shawn Thomas received a bachelor’s in electrical engineering from the University of Illinois, Urbana-Champaign and master’s and PhD in electrical engineering from UCLA, and is the director of technology & applications for the Epsilon product line at ASM America, 3440 E. University Dr, Phoenix, AZ 85034 USA; 602-470-5753; email shawn.thomas@asm.com.

    Matthias Bauer received a diploma in physics from Eberhard-Karls U. in T??bingen, Germany, and a PhD in electrical engineering from the U. of Stuttgart, Germany. Hs is a senior staff scientist at ASM America, Phoenix, AZ USA.

    Matthew Stephens received a PhD in physical chemistry from the U. of Wisconsin-Madison and an MBA at INSEAD, Singapore. He is the COO of Voltaix LLC, P.O. Box 5357, 197 Meister Avenue, Branchburg, NJ 08876 USA; email mstephens@voltaix.com.

    John Kouvetakis received his PhD at the U. of California at Berkeley and a professor in the Department of Chemistry and Biochemistry at Arizona State U. GWC B30/30A D-202E, Tempe, AZ 85287 USA; email jkouvetakis@asu.edu.