Progress towards the merger of compound semiconductors and silicon


Judging by the 2008 International Electron Device Meeting (IEDM), momentum continues to build toward eventual integration of compound semiconductors and mainstream silicon technology. Just a few years ago, there were few papers and most were specialized towards stand-alone chips for radio frequency or high voltage power applications. This past year, the conference had multiple sessions and marked progress towards some of the key challenges.

Mike Mayberry, Intel, Hillsboro, OR USA

As a recap, compound semiconductors are interesting within the context of integration into mainstream silicon technology because their high mobility allows substantial voltage reduction while keeping performance constant. Because voltage swing directly affects power, the revolutionary promise is devices with a 10?? better power-to-performance ratio vs. the equivalent mainstream silicon devices. Nevertheless, challenges to achieve this objective are extreme; here are five key challenges:

  • Build compound semiconductor devices on silicon substrates. That would allow us to reuse the highly refined silicon infrastructure including 300mm wafers, and down the road, gives us the option of integrating a few specialized devices with a sea of silicon devices.
  • Find a suitable high-k gate dielectric. Due to the different surface, the silicon high-k solution won’t work as is, but we can leverage knowledge we gained to help guide us. The appropriate gate dielectric saves power and allows further channel scaling.
  • Build a high-performance p-channel device to go with the existing n-channel. This is needed to have power-efficient complementary logic, though some special circuits can get by with just one type.
  • Build enhancement mode devices. Most existing work is based on depletion mode, where a voltage is applied to shut them off. Power efficiency demands that those devices be normally off.
  • Make them small enough to compete with silicon transistor densities. If we stop at integrating only a few specialized devices then this is not needed; however, we won’t reap the full benefit of the technology.

Reported progress to date

Intel reported fabrication of a high-performance n-channel device on a silicon substrate at IEDM 2007 [1]. This was fabricated using molecular beam epitaxy (MBE) to create a graded buffer that trapped dislocations and provided lattice match for the InGaAs quantum well layer. Those devices showed >10?? improvement in power for equivalent performance or >2?? improvement in performance at same power, highlighting the promise of this integration.

This past year, an invited paper from Hong Kong University of Science and Technology showed functional devices fabricated on silicon using metal-organic chemical vapor deposition (MOCVD) instead of MBE [2]. While the devices had much lower performance compared to those made with MBE, MOCVD is potentially a more friendly approach to high-volume manufacturing. The speaker commented that anything done with MBE can eventually be done with MOCVD.

The second challenge is to integrate a suitable high-k dielectric into the device, and 2009’s IEDM had a whole session devoted to fabrication of III-V MOSFETs with high-k dielectrics. Researchers are currently investigating multiple approaches, combining both basic material science as well as engineering. Two papers from Purdue University [3, 4] showed creation of InGaAs MOSFETs, characterization of interface trapping, and then relating the results back to model calculations. Other papers examined techniques for cleaning the native oxide and then passivation of the surface prior to ALD deposition of a suitable high-k film [5, 6]. To date, the best-performing devices still have large equivalent oxide thickness, so much more work is needed to improve the quality of materials and interfaces to achieve equivalent coupling performance compared to state-of-the-art silicon devices. Figures of merit to watch include equivalent oxide thickness (EOT) and channel mobility.

Figure 1. SEM micrograph of a 40nm gate length InSb p-channel compressively strained QWFET with gate air-bridge suitable for RF characterization.
Click here to enlarge image

The third challenge is a high-performance p-channel device to enable complementary logic. For most III-V materials the hole mobility is 20???100?? lower than the electron mobility. We can make the p mobility higher by copying a technique from silicon processing, add strain to the material. Strain works by changing the band structure to favor a population of light holes instead of the mixture of heavy and light holes in unstrained material. This past year, Intel presented a paper [7] showing the application of strain to a p-channel quantum well. A top down view of the device is shown in Fig. 1. Application of ∼2% strain raised the mobility to >5?? higher than strained silicon and the fabricated device achieved 140GHz in fT, as illustrated in Fig. 2. The fabrication technique used was MBE, similar to that used to grow the n-channel devices.

Figure 2. LG=40nm device achieves fT=140GHz at VCC=0.5V, the highest reported for III-V p-QWFET.
Click here to enlarge image

Silicon CMOS uses enhancement mode devices, meaning those devices are turn on when voltage is applied. Many III-V devices are of the depletion mode type, meaning an applied voltage shuts them off. Enhancement mode can be achieved by geometric and/or material engineering. A paper from MIT [8] showed fabrication of enhancement mode devices that matched the best reported depletion mode performance and were the first devices to benchmark with >600GHz for both fT (unity current gain frequency) and fmax (unity power gain frequency). These devices had gate lengths down to 30nm, roughly comparable to leading-edge silicon in production today.

Looking ahead

Pausing at this point, let us assume these four challenges can be solved and are suitable for high-volume manufacturing. If we are able to put III-V devices on the same chip as a sea of silicon devices, then we can add the unique capability that III-Vs bring to existing product designs. For example, RF chips today use III-Vs for high-frequency performance and adding this technology to silicon might allow use of multiple radios with better power and performance. Similarly, III-Vs are more efficient at emitting light than silicon and adding optical interconnects to a silicon chip would (in principle) become easier.

The progress to date is sufficient to start asking what those products would look like and whether they are better than solutions we have today. If we can make devices that act like conventional CMOS circuits and we can make them on silicon, then we can consider devices that have III-Vs used in blocks for either high performance or in blocks with low operating voltage (0.5 vs. 1V for silicon) and mix them with the more dense silicon transistors. Products built on this process should suit handheld devices: low-power blocks would extend battery life in addition to the integrated radio advantage. While still a few years away, these capabilities could enable exciting new products which are difficult to achieve today.

The last challenge is to achieve comparable density (=cost). Even the smallest gate channel devices fabricated today still have big features and a large footprint. It will take considerably more work to enable small devices and it is unclear whether those will be fabricated as planar devices (those best studied to date) or as non-planar devices [9] to increase the density. Although we have made good progress to date, we are still far away from solving this challenge and this may ultimately limit the penetration of III-V technology.


Each year, IEDM papers mark progress against the key challenges and next year should bring further progress. We expect continued progress in devices fabricated unconventionally, for example thinner buffers for those grown on silicon, better on/off ratios, and continued scaling of physical dimensions. Benchmark and modeling activities will help define the best use for these devices. In parallel, work to explore different manufacturing techniques is just beginning to ramp and those results should start to be reported in the coming year. While the ultimate future is difficult to predict, we can safely say that these are exciting times for this field.


  1. M. K. Hudait et al., “Heterogeneous Integration of Enhancement Mode In0.7Ga0.3As Quantum Well Transistor on Silicon Substrate using Thin (=2µm) Composite Buffer Architecture for High-Speed and Low-voltage (0.5V) Logic Applications,” IEDM Tech. Dig., 2007. pp.625-628.
  2. K. M. Lau et al., “AlInAs/GaInAs mHEMTs on Silicon Substrates Grown by MOCVD,” IEDM Tech. Dig., 2008. pp.723-726.
  3. Y. Xuan et al., “High-Performance Surface Channel In-Rich In0.75Ga0.25As MOSFETs with ALD high-k as Gate Dielectric,” IEDM Tech. Dig., 2008. pp.371-374.
  4. D. Varghese et al., “Multi-Probe Interface Characterization of In0.65Ga0.35As/Al2O3 MOSFET,” IEDM Tech. Dig., 2008. pp.379-382.
  5. T. H. Chiang et al., “Approaching Fermi Level Unpinning in Oxide-In0.2Ga0.8As,” IEDM Tech. Dig., 2008. pp.375-378.
  6. Y. Sun et al., “Scaling of In0.7Ga0.3As Buried-Channel MOSFETs,” IEDM Tech. Dig., 2008. pp.367-370.
  7. M. Radosavljevic et al., “High-Performance 40nm Gate Length InSb P-Channel Compressively Strained Quantum Well Field Effect Transistors for Low-Power (VCC=0.5V) Logic Applications,” IEDM Tech. Dig., 2008. pp.727-730.
  8. D.-H. Kim et al., “30nm E-Mode InAs PHEMTs for THz and Future Logic Applications,” IEDM Tech. Dig., 2008. pp.719-722.
  9. R. Chau, et al., “Advanced Depleted-Substrate Transistors: Single-gate, Double-Gate and Tri-gate,” Extended Abstracts of the International Conference on Solid-State Devices and Materials (SSDM), 2002. pp. 68-69.

Mike Mayberry received his bachelor’s in chemistry and mathematics from Midland College and his PhD in physical chemistry from the U. of California, Berkeley. He directs technology research and is VP within the Technology and Manufacturing Group at Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR, 97124 USA; For questions or inquiries, please contact Megan Langer at: ph.: 503-712-4305; email