Issue



Codesign enables rapid development and high performance


04/01/2009







The benefits of chip/package and chip/package/board codesign flows are realized only through early and frequent communications. Earlier access to and collaborative negotiation of requirements, as well as parallelization of design tasks, are key to schedule decreases, performance increases and cost reductions.

Brad Brim, Sigrity, Santa Clara, CA

T raditional package design is initiated only afTer chip design is completed. The chip design team passes a bump map, netlist, and general electrical constraints to package designers, allowing the package physical design and electrical verification processes to begin. Only afTer the package design is completed and electrical constraints verified is a ball map and netlist provided to board designers. However, the time required for this serial development process (Fig. 1a), has become prohibitive due to the rapid time-to-market concerns for modern electronics. Serial development also bounds achievable performance levels because there’s little opportunity for feedback from one design team to the other. This absence of collaborative feedback drives downstream design teams toward unnecessarily complex implementations to achieve performance targets, increasing end-product cost.


Figure 1. Codesign serves to parallelize previously serial design flows.
Click here to enlarge image

Given these factors, consideration of codesign is now commonplace within the chip, package, and board design communities. Codesign refers to a simultaneous design process across two or more physical domains of what is ultimately a chip/package/board system. Its objective is to shorten design cycle times and ensure high-performance systems. In codesign, the classical serial design flow is parallelized, as shown in Fig. 1b. Package design begins well before the chip design is complete, and board design also begins prior to the availability of packaged chips. Parallel design speeds development and leads to higher-performance designs implemented at lower cost. Package designers are stuck in the middle, needing to satisfy chip and PCB requirements. This is especially true for ASIC packaging, where both package and chip designs are driven by specifications from the intended board application, rather than chip bump maps.

In the past, chip design teams perceived package design as an independent task subordinate to, and ofTen subsequent to, chip design for both in-house and outsourced package design. Two drivers now motivate chip teams to communicate with package teams earlier in the packaged chip flow. First is the growing business imperative for feasibility studies to determine if final packaged chips meet cost and performance targets within the development window. Feasibility is not just for project management, increasingly supporting the request-for-quote process when internal chip design management teams interact with external customers. The second driver is implementation, a step that must proceed quickly with little risk for unforeseen delays. Communication between chip and package design teams is necessary during the back-end chip design flow once floor planning has begun. Performance and cost tradeoffs between chip-level decisions and package-level design implications can be considered earlier if design tasks are progressing in parallel for chip and package.

The industry has experienced a proliferation of chip-to-chip, multi-Gbit, high-speed serial channels, and a continued increase in parallel bus data rates. Package designers must know which signal channels are performance-critical to ensure high-quality signal paths and adequate local power delivery, which helps avoid crosstalk and SSN. A hastily designed package hinders system performance. Unfortunately, redesigning a package to compensate for inadequate performance consumes many weeks and cost. Development delay of even one calendar quarter destroys thin profit margins. Unnecessarily complex and expensive package implementations also impact profit margins because package manufacturing costs are on par with chip costs.


Figure 2. Feasibility studies augment serial design flows but planning solutions and collaborative information exchange enable full codesign chip/package codesign flows.
Click here to enlarge image

Figure 2a shows how many early chip/package codesign flows are implemented. Package designers apply preliminary specification of physical and electrical requirements to support feasibility investigations. These specifications may include guesses for bump map regions, power requirements, high-speed I/O regions, and electrical constraints. Package engineers then examine considerations such as stack-up requirements, wirebond feasibility, routability for signals with impedance and loss considerations and, finally, power planes and the potential need for in-package decoupling capacitors. Planning tools and pre-layout electrical analysis support these considerations.

The planning process was once spreadsheet-based, but a class of commercial solutions is available to address planning challenges across multiple physical domains in a more automated manner. These tools also provide a transition to early implementation of both chip and package physical designs, as represented in the righthand portion of Fig. 2a. Pre-layout electrical analysis provides requirements that drive stack-up choices, such as static and dynamic power delivery noise analysis and what-if feasibility studies for increasingly common multi-Gbit serial channels.

As chip designs progress to the back-end and implementation begins, more detailed planning and electrical analyses are enabled between chip and package. As shown in Fig. 2b, the gap between feasibility and implementation must shrink for a more thorough chip/package codesign flow by exchanging information as soon as it becomes available. For example, as floor planning progresses, chip designers finalize the definition of functionality for regions of the chip and approximate their power delivery requirements. With this information, package teams begin power delivery network design. This may seem like a minor task, but with the power requirements of high-speed serial I/O drivers and the current draw of simultaneous switching of DDR buses, power integrity can drive package electrical behavior.

The early design of robust package power delivery significantly eases the task of assuring package signal integrity because poor power delivery is directly reflected as poor signal integrity — the two concepts are inseparable. DC and AC power delivery solutions are commercially available for both pre-layout and post-layout electrical analysis of packages. The best of these solutions enable analysis of the entire physical domain, i.e., the entire chip, package or board. Electrical models of only a few signal nets ofTen miss global coupling and voltage noise issues. Electrical models ust have adequate bandwidth to accommodate the signals present in the system. Commercially available solutions span the range of package model extraction applications, from low- to high-speed, multi-Gbit signals.

Increased communication early in the design flow leads to schedule compression, especially when outsourcing. The issue is time delay between a physical or electrical requirement being passed to the package design team and their ability to respond with a design update. In-house package teams usually respond within a week, but the time can double or triple for outsourced package design. It is more important for chip design companies without in-house package design teams to embrace the concept of codesign. Waiting for communications to occur later in the codesign flow is reckless because only a few iterations of design between the chip and package team put profit margin at risk due to schedule delays. The most successful design teams communicate early and ofTen.

System-level chip/package/board codesign is an extension of chip/package codesign. The same motivation and benefits exist: faster time to market with lower cost and increased performance. Large companies that have in-house design teams for each of these three physical domains are logical adopters of codesign flows, but startup chip companies and package design houses also can realize the benefit of such flows.

Designing an ASIC is a good example for consideration of a chip/package/board codesign flow. ASIC specifications ofTen are driven by board- rather than chip-level specifications. The system design customer specifies ball maps, static and dynamic power delivery bounds and signal content, as well as serial and parallel I/O locations. These specifications for the packaged ASIC may be negotiable early during system design, less so as implementation progresses. This is analogous to the early feedback package designers provide chip teams for chip/package codesign. Designers collaboratively evaluate performance budgets such as noise or loss during early analysis of chip and package, and make tradeoffs not only across chip/package domain boundaries, but also between the board system and the packaged ASIC.


Figure 3. Low -performance net length matching is avoided in both package and board through codesign consideration of electrical effects that cancel across the package/board boundary.
Click here to enlarge image

Multi-domain planning solutions can provide even greater value for system-level designs because they merge three individual design databases into a single, easily accessed, and easily manipulated database. Designers can investigate routing topologies and block placement tradeoffs. The planning process provides an analytical basis for negotiating ball map specifications and even electrical constraint specifications such as high-speed differential nets (diff pairs) in a chip/package/board system. Typical specifications for an ASIC require deskewing of each diff pair within the ASIC relative to the package/board physical interface. To accomplish this, package designers match the net lengths, which makes routing more difficult and ofTen requires a meander in the shorter net (Fig. 3). Designers should avoid this type of geometry if possible because its high-speed electrical performance is poor. The solder ball location for the shorter package net is usually toward the center of the package relative to the solder ball for the longer net. This implies that the same deskewing is required on the board for the net that was longer in the package. If both board and package designer agree to avoid deskewing, routing is easier and high-speed performance is better. Codesign collaborative exchange between package and board teams enables easier routing and increased high-speed performance with a simply negotiated physical constraint of net length and solder ball position for diff pairs.

To acheive system-level performance targets, electrical analysis of the chip/package/board system must be verified throughout the codesign flow. Analogous to the planning and implementation process discussed for chip/package codesign, chip and board designers should specify, negotiate with package designers and finalize system-level regions for the functional blocks, as early as possible in the codesign flow. This approach enables initial package physical designs to be generated, which supports more complete electrical analysis and electrical model generation. System designers apply these electrical models to perform static and dynamic noise power integrity analyses for power nets, and perform signal integrity analyses for the high-speed serial and parallel channels.


Figure 4. Chip-centric and board-centric electrical analysis require different levels of package model detail and the physical domain boundaries.
Click here to enlarge image

Package and board designers commonly generate electrical models to support chip-centric analysis, while models from the chip and package teams support board-centric electrical analysis. A key aspect of these multiple physical domain electrical analyses is the level of detail, or resolution, required for the various electrical models. As the early design is preliminary and stabilizes during the codesign flow, the level of detail required for electrical models begins at a low level and increases during the flow. The one-time generation of a single electrical model typically is not possible and, therefore, electrical analysis tools are applied throughout a codesign flow.


Figure 5. Applying a package electrical model with too low resolution incorrectly localizes and dampens voltage noise on the chip.
Click here to enlarge image

The resolution of package electrical models required for chip-centric analysis is different than for board-centric analysis, as shown in Fig. 4. For example, chip designers require low resolution model information at the package/board interface, but higher resolution of model information at the chip/package interface. As seen in Fig. 5, package models with inadequate resolution at the chip/package interface lead to an unrealistically low prediction of voltage noise effects and can result in unexpected product failure. Again, the package engineer is stuck in the middle, serving two sets of potentially conflicting requirements. Electrical analysis tools are available for package model extraction to serve variability requirements for package model resolution — both increasing resolution as the codesign flow progresses, and variations of model requirements for chip-centric or board-centric electrical analysis.

Conclusion

Package design classically was an afTer-thought in the serial design of packaged chips. However, the benefits of chip/package and chip/package/board codesign flows are realized only through early and frequent communications. Earlier access to and collaborative negotiation of requirements, as well as parallelization of design tasks, are key to schedule decreases, performance increases and cost reductions.

Brad Brim has product marketing responsibilities for Sigrity in the area of package and PCB extraction. His 20 years of experience include various roles in development, applications and marketing of EDA solutions for high-speed components, circuits and systems. email: bradb@sigrity.com.