Combinatorial PVD and ALD workflows for cost-effective R&D
Imran Hashim, Monica Mathur, Prashant Phatak, Ron Kuse, Sandra Malhotra, Sean Barstow, Sunil Shanker, Tony Chiang, Intermolecular Inc., San Jose, CA USA
Special workflows using combinatorial technology applied to physical vapor deposition (PVD), atomic layer deposition (ALD) and wet processes can be utilized for applications including development of alternative non-volatile memory and metal gate high-k dielectrics for high-performance logic. The new technology is compared with conventional techniques in testing time, identification of optimal solutions for new materials and, consequently, in R&D cost efficiency for research and development.
With materials innovation driving recent logic and memory scaling in the semiconductor industry, High-Productivity Combinatorial (HPC) technology can help find optimum solutions faster and cost-effectively. Specifically, the use of combinatorial approaches and application-driven workflows can increase learn rates, improve R&D efficiency, and earn higher overall returns on research investments.
The combinatorial approach
The guiding principle of HPC methodology is to ask and answer only those questions necessary at each stage of development. The three pillars that can accelerate learning rates by several orders of magnitude are massively parallel processing — conducting dozens or hundreds of automated experiments in parallel on a single substrate using miniaturization and site isolation; throughput-matched characterization, with proprietary test chips and automated metrology including e-test; and centralized data collection, management, analysis and reporting via an informatics software.
Phase change memory as flash replacement
Chalcogenide alloys such as GeSbTe exhibit a reversible amorphous-crystalline transition depending upon heating rate. This makes them attractive for flash memory replacement at the 32nm node or below because significant challenges exist with scaling of traditional flash memory. However, challenges abound with integrating chalcogenide materials with conventional semiconductor processes, including deposition, polishing, and/or etching of these materials as well as thermal budgets for back-end processing. Also, various potential chalcogenide alloys exist, as do integration schemes, making it impractical to effectively evaluate all promising combinations of material, process, and integration sequences. This is a good example of the type of problem that is well suited to the combinatorial approach.
For non-volatile memory applications such as phase-change memory (PCM), some of the critical HPC workflow components include site-isolated depositions using PVD or ALD, custom-designed test chips, material characterization, and automated electrical testing. One critical aspect of non-volatile memory workflows is the ability to deposit the material(s) of interest in a manner that creates isolated individual unit “memory cells“ that are uniquely testable without patterning.
Using an HPC PVD chamber, we developed a workflow that allows up to ˜40 precisely controlled chalcogenide alloy compositions to be deposited in discrete site-isolated areas on a single wafer and tested for electrical and material properties. The PVD chamber has up to four different sputter guns that can be used for RF, DC or pulsed-DC sputtering of individual elements in the chalcogenide alloys, for example, Ge, Sb and Te. Site-isolated deposition capability is achieved using a combination of pedestal rotation (about multiple axes) and an aperture/shutter assembly. Material characterizations include film thickness and composition measurements using X-ray fluorescence, and post-crystallization microstructural analysis using X-ray diffraction. The electrical characterization of these site-isolated areas on a blanket wafer includes in situ sheet-resistance measurement vs. temperature of the different chalcogenide compositions.
Figure 1. Ternary Phase Diagram for GST and compositions along Sb2Te3-GeTe pseudo-binary tie line deposited using HPC PVD on a single wafer shown in the inset.
The metrology tools for this electrical and material characterization were optimized for throughput comparable to that of the deposition tool. In this workflow, basic material properties such as crystallization temperature, final and intermediate crystalline phases, if any, can be obtained for each of the ˜40 different chalcogenide alloys on one wafer.
Figure 1 shows a wafer with 12 GeSbTe compositions along the GeTe-Sb2Te3 pseudo-binary tie line that were deposited on a single 200mm wafer using HPC PVD. Figure 2 shows plots of the in situ sheet-resistance vs. temperature for these GeSbTe compositions, providing accurate crystallization temperature, transition abruptness and identifying multiple crystalline phases (such as for GST 225, which goes through an intermediate fcc phase before the final hcp phase). Finally, informatics software analyzes and archives the large volume of data generated from these experiments, enabling timely decisions for the next set of experiments.
The workflow described is appropriate for primary screening to compare intrinsic properties of different chalcogenide alloys. However, electrical switching of these alloys in a ˜30 ?? 30nm cell will depend on other factors, such as thermal conductivity of adjacent materials, electrode heater material and the architecture of the cell. A secondary screening workflow for this application requires a proper test-chip design with the bottom electrode/heater already patterned at the appropriate dimensions, followed by combinatorial site-isolated deposition of the chalcogenide alloys and top electrode using the PVD chamber. The dimensions of the top electrode and switching material may be defined using physical masking, and are typically on the order of ˜200µm, allowing direct contact with the testing probe. One of the advantages of this workflow is that no patterning is required after the deposition of the chalcogenide and top electrode, accelerating learning cycles and allowing switching performance to be studied independent of etch or strip interactions with the chalcogenide alloys.
Using this secondary screening workflow, single-cell switching characteristics of up to 40 chalcogenide alloys can be compared using one wafer. When combined with site-isolated deposition and throughput-matched characterization, the proper HPC test chip allows for rapid screening and testing of many unique NVM cell types. The final stage in optimum chalcogenide alloy selection compares a few pre-screened compositions for ease of integration, reliability, and cycling performance on 1k or larger memory arrays. Exploring a larger set of compositions using combinatorial workflows, helps researchers find the optimum composition for a particular application, reducing the cost associated with wafers and sputter targets.
High-k dielectrics and metal gates for logic transistors
Another example in which combinatorial ALD and PVD workflows can be used is for finding optimum high-k dielectric and metal gate solutions for high-performance logic transistors. Assessing the effective work functions (EWF) for given high-k dielectric metal-gate stacks for PMOS and NMOS transistors is a critical step for selecting the right materials. This assessment can be difficult using simple C-V measurements because varying amounts of fixed charges for different high-k dielectric thicknesses on different wafers can also affect the flat-band voltage (Vfb). One way to address this is by using a terraced oxide wafer with varying SiO2 thickness bands underneath the high-k dielectric so that Vfb variation with different EOTs can be obtained from a single wafer, and extrapolated to assess the EWF for a single high-k dielectric-metal stack. 
We report here a much higher throughput workflow using our combinatorial wet and dry capabilities. In this workflow, EWF for multiple high-k dielectric and metal gate stacks can be extracted from a single wafer. This increases the learning rate and probability of finding the best high-k metal gate combination while reducing the cost of experiments.
Figure 3 illustrates a MOS capacitor-based combinatorial EWF workflow that started with etching of thermally grown silicon oxide. This created a terraced oxide with thicknesses of 1-10nm in select areas of the same wafer using Intermolecular’s combinatorial wet workflow described elsewhere. This was followed by HfO2 high-k deposition using a metal-organic precursor and ozone as oxidizer for ALD. Next, PVD was used to deposit the metal electrodes such as TiN or TaN. The wafer was subjected to thermal treatments post-dielectric deposition as well as post-metal deposition. To define MOS capacitors, physical masking was used during metal electrode deposition to form capacitors ˜200µm in diameter. C-V and I-V measurements were made using a high-throughput automated electrical tester that completed this workflow.
Using programs such as NCSU C-V modeler , the Vfb and EOT were extracted from the C-V curves. Finally, this Vfb was plotted versus EOT for different oxide thicknesses, to obtain an EWF using the methodology described by H.C. Wen et al.4 Figure 3c shows an example of EWF extraction for PVD TaN/ALD HfO2/SiO2/Si using this workflow. The resulting EWF of 4.53eV is similar to that reported for this HKMG stack . This workflow was also used to assess impact of NMOS and PMOS dielectric cap layers, e.g., La2O3 and Al2O3 on EWF and EOT. Further results with different dielectric cap layers and with high-k films deposited using a combinatorial ALD chamber will be reported at the 2009 MRS Spring Meeting.
Combinatorial PVD can be used to vary the metal electrode depositing alloys of different compositions in site-isolated regions. C-V curves for MOS caps with different metal electrode compositions for a binary alloy were deposited using PVD, demonstrating how the work function can be tuned from Si mid-gap to valence-band edge by varying alloy composition (Fig. 4).
Using a combination of HPC ALD, PVD, and wet capabilities, EWF of multiple high-k dielectric and metal electrode combinations can be obtained using a single wafer. Once this primary screening on MOS capacitors yields the high-k dielectric metal gate combinations that meet EOT, Jg, and EWF requirements, promising solutions can be compared using MOSFETs for integration compatibility and other electrical parametrics.
The efficiency improvements seen in the case studies presented are a direct result of being able to customize a workflow to address a specific technology challenge instead of attempting to work only within the constraints posed by traditional R&D approaches and high-volume manufacturing tools. The proper use of application-specific workflows, guided by the principle of asking and answering only those questions relevant at each stage of development using the combinatorial method, can result in faster learn rates, a more complete data set and more highly optimized solutions while at the same time greatly reduced costs.
The authors would like to acknowledge the assistance of colleagues in Intermolecular’s ALD/PVD technology and engineering groups, without whose support this work would not have been possible. High-Productivity Combinatorial is a trademark of Intermolecular Inc.
- S. Lai, T. Lowery, “A Chalcogenide-based Device with Potential for Multi-state Storage,“ Tech. Digest, Int. Electron Devices Meeting, p. 803, 2001.
- J.I. Lee et al., “Highly Scalable Phase Change Memory with CVD GeSbTe for Sub-50nm Generation“, VLSI Tech. Digest, p.102, 2007.
- K. Mistry et al., “A 45nm Logic Technology with high-k+Metal Gate Transistors, Strained Silicon, 9 Cu Interconnect Layers, 193nm Dry Patterning, and 100% Pb-free Packaging,“ Tech. Digest, Int. Electron Devices Meeting, p.247, 2007.
- H.-C. Wen et al., “Comparison of Effective Work Function Extraction Methods Using Capacitance and Current Measurement Techniques“, IEEE Elect. Device Lett., Vol. 27, pp. 598-601, 2006.
- A. Srivatsa, P. Zhang, N. Kalyanker, A. Karumcheti, Z. Fresco, “Accelerating Semiconductor R&D with Combinatorial Technology,“ Solid State Technology, October 2007.
- N. Yang, W. Henson, J. Hauser, J. Wortman, “Modeling Study of Ultrathin Gate Oxides using Direct Tunneling and Capacitance,“ IEEE Trans. Electron Dev. 47 11, pp. 2161-2166, 2000.
- K. Choi et al., “Effective work function modification of atomic-layer-deposited-TaN film by capping layer,“ Appl. Phys. Lett., Vol. 89, 032113, 2006.
Imran Hashim received his PhD in materials science from the California Institute of Technology, and is senior director of Dry Programs at Intermolecular, Inc., 2865 Zanker Road, San Jose, CA 95134. Ph. 408/416-2268, email: email@example.com.
Monica Mathur received her PhD in chemical engineering from the U. of California, Los Angeles and is a process engineer in dry programs at Intermolecular Inc.
Ron Kuse received his master’s in materials science & management from the Massachusetts Institute of Technology, and is a senior member technical staff at Intermolecular Inc.
Prashant Phatak received his PhD in materials science from the U. of California at Berkeley and is a director of technology at Intermolecular Inc.
Sandra Guy Malhotra received her PhD in materials science and engineering from the U. of Michigan and is a director of technology at Intermolecular Inc.
Sean Barstow received his PhD in chemical engineering from the Georgia Institute of Technology and is product marketing manager of Dry Programs at Intermolecular Inc.
Sunil Shanker received his master’s in mechanical engineering, and is pursuing an MBA at the Haas School of Business, UC Berkeley. He is a project manager of dry programs at Intermolecular Inc.
Tony Chiang received his PhD in materials science from Massachusetts Institute of Technology, and is CTO at Intermolecular Inc.