Issue



3D integration with TSV: temporary bonding and debonding


03/01/2009







Stefan Pargfrieder, Jürgen Burggraf, and Daniel Burgstaller, EV Group, St. Florian/Inn, Austria. Mark Privett and Amandine Jouve, Brewer Science, Inc., Rolla, MO USA. David Henry and Nicolas Sillon, CEA LETI, Minatec, Grenoble Cedex 9, France.

Making reliable through-die interconnects for 3D wafer stacking usually requires a reduction in wafer thickness and therefore improved wafer handling. Temporary wafer bonding adhesives are becoming increasingly important for wafer-level bonding. The technologies must offer adequate flow properties, mechanical strength, thermal stability, chemical resistance, and easy debonding and cleaning.

As the microelectronics industry promotes emerging and future applications, new and improved methods will be necessary to meet the associated manufacturing challenges. Emerging products and applications, such as heterogeneous integrated chips, high-density memory devices, or radio-frequency identification (RFID) tags, along with the advent of new advanced packaging technologies for a variety of products — logic, memory, CMOS image sensors (CIS) — require new manufacturing technologies, including through-silicon via (TSV), novel 3D integration schemes, and ultra-thin wafer handling and processing capabilities.

Making reliable through-die interconnects for 3D wafer stacking technologies usually requires a reduction in wafer thickness, which, when combined with a large wafer diameter, necessitates new wafer handling requirements. Among the different wafer-level bonding techniques, temporary wafer bonding adhesives are gaining importance in the microelectronics and advanced packaging industries.

Temporary bonding and debonding technologies, in combination with new-generation adhesives, must possess a variety of properties to be integrated into all the required processes, including adequate flow properties, mechanical strength, thermal stability, chemical resistance, and easy debonding and cleaning.

A removable high-temperature adhesive developed by Brewer Science meets these requirements for reliable TSV processing. Applying recent temporary bonding and debonding developments and achievements with respect to ultra-thin wafer handling and processing, TSVs were formed in a 70µm thinned silicon wafer.

Here, TSV processing encompasses backgrinding and stress release, via-etching, insulation, as well as metallization and electrical characterization after debonding.

EVG and Brewer Science worked jointly to develop a temporary bonding and debonding process using established processes and equipment. The result enables temporary bonding of a device wafer to a rigid carrier substrate and allows thinning as well as a range of subsequent processes needed for TSV formation. This article provides an updated overview of temporary bonding techniques and offers details of applied processes needed for TSV generation.

Temporary bonding basics

A typical process flow for temporary bonding first involves fully processing the device wafer on the front side. Subsequently, the carrier wafer and/or the device wafer is coated with an adhesive. Both wafers are then transferred to a bond chamber, where they are carefully centered and vacuum-bonded at elevated temperatures. The selection of the appropriate coating process and technology is influenced by the wafer topography that must be embedded by this material. Using high-performance HT-Series material from Brewer Science, for wafer topographies less than 20µm, a single spin-coating process is sufficient for coating, followed by a baking step to remove the solvent. For topographies greater than 20µm, spin-coating both device and carrier are used to planarize and cover features. For topographies beyond 40µm, such as wafers with bumps or solder balls as well as wafers that have chips bonded onto their surface (via a chip-to-wafer, C2W, integration scheme), for example, spray coating technology is used to planarize and cover features.

The various described coating schemes are all performed within a single-wafer coating chamber, which includes simultaneous integrated spin- and spray-coating capabilities.*

Following temporary bonding, the wafer stack undergoes a via-last TSV backside process. Finally, the thinned device wafer is debonded from the carrier wafer.**

Bonding process

Glass or silicon carrier wafers can be used for the temporary bonding process. As a first indicator for carrier selection, the post-bond bow of the stack was characterized.

After chilling, the bow on the two bonded pairs with 15µm of adhesive was measured on a DEKTAK tool. Results show a higher bow value for silicon-to-glass bonding due to a mismatch of the coefficients of thermal expansion (CTEs) of these materials. On a silicon to glass bond, the bow was less than 200µm; on silicon-silicon bonds, the bow was about 30µm. This more extensive bowing could lead to difficulties in handling as well as inhomogeneties during subsequent post-bond processing. Furthermore, a comparison of the wafers’ thermal properties and the fact that silicon has a high thermal conductivity (more than 100?? that of borofloat glass) enables shorter process and cycle times for steps that involve temperature treatments by using silicon carriers.

Thinning process

The high bond strength of device wafer to carrier wafer allows for a successful thinning and grinding process to 20µm or thinner with lowest thinned substrate total-thickness variation (TTV, <3µm) at the same time. To facilitate highest yielding handling of the thinned stack, we demonstrated that an edge extrusion could also be processed before thinning.

TSV process integration

The process steps carried out for TSV formation are applied on the device wafer with deposited SiO2 and Al finish. The via-last process was chosen as it is currently a commonly known and accepted process[2] used for various applications (Fig. 1).


Figure 1. Main steps of the TSV process flow.
Click here to enlarge image

The post-bond process for via-last technology includes:

  • Backgrinding and stress relief by chemical mechanical polishing (CMP). The final targeted thickness of the silicon was 70µm, including an edge extraction (1.5mm wide).
  • Via dry etching (classical Bosch process) and insulation using a low temperature SiO2 PECVD at 150°C.
  • Via metallization by electroplating and passivation. The final copper protection is done using a photosensitive polymer (BCB 4024 from Dow Chemical). This material requires a long curing bake, which has been processed either at 200°C during 10 hours or 250°C during 1 hour under N2 environment.
  • Debonding and cleaning of the thinned wafer and the carrier. The thinned wafers have been debonded at 180°C and cleaned with an appropriate solvent on the automated EVG tools.

The aluminum deposition on the wafer’s front side enabled electrical characterization of the vias before and after debonding to evaluate the process yield.

Results

All the wafers temporarily bonded on silicon or borosilicate successfully underwent the entire TSV process. Thinning and polishing of the active substrate down to 70µm yielded good quality. No delamination or degradation of the temporary bonding layer was observed with borosilicate or silicon carriers, even after the final high-temperature via passivation step.


Figure 2. Microsope image of 65µm vias and rerouting.
Click here to enlarge image

The aspect ratio 1:1 TSVs before debonding can be seen in Fig. 2.

Debonding process

Upon completion of TSV and backside signal distribution or other circuit creation, the final thinned device must be separated from the carrier, cleaned, and eventually singulated for further use.

A thermo-mechanical activated slide-off technique was applied to debond the device wafer from carrier wafer. The thermal-assisted debonding system consists of a compliant chucking system to protect the created topography on the back side of the device wafer while heating the stack to a temperature higher than the softening point of the temporary bonding material. For debonding, the wafer stack is fixed in an appropriate debonding module on both sides with a compliant vacuum chucking system and uniformly heated. When debonding temperature is reached, the two wafers are slid apart. The debonding module is designed so that the wafers are fully supported over the whole area and kept flat and stress-free during the debonding procedure.

Typical debond processes based on Brewer Science material are carried out at temperatures ranging from 180° to 220°C on the EVG tool. After the wafers are separated, the thin wafer is transferred to a single-wafer cleaning chamber, where remaining adhesive is removed with an appropriate solvent. This approach allows fast, residual-free adhesive removal using a minimal amount of cleaning solvent, reducing consumables use and costs.

Using a process similar to that of spin coating, the device wafer is transferred to a wafer-sized chuck on a spin coater. An accepted solvent is dispensed on the device wafer or carrier and left to soak. During soaking, the solvent is agitated using a proprietary tool developed to better dissolve the polymer. As the polymer dissolves, the wafer is spun and sprayed with additional solvent to allow complete cleaning.


Figure 3. Debonding process flow includes debonding cleaning and the transfer of the thin wafer into various output formats.
Click here to enlarge image

A special end-effector or spinner chuck supports the wafer throughout all process steps until it is transferred to the film-frame carrier or other output formats. Figure 3 shows the overall process flow, starting with wafer stack debonding, followed by cleaning and unloading the thin wafer into free selectable output formats. Flexible separation of the individual process steps enables individual use and/or a combination of process approaches.

Electrical testing

The debonding and cleaning processes were performed successfully. No scratches or degradations of the patterns were observed on either thinned wafer faces. The bottom of the TSV, which was as thin as 9µm, did not crack during debonding and cleaning. The bow quantity of the wafer after debonding is due to the residual stress of the thinned silicon wafer.

Finally, an electrical set up was designed to evaluate the TSV functionality and calculate the electrical yield of the device. The test was a short daisy chain between the Al frontside layer and two backside TSVs.

Electrical contact on the 1135 dies of the wafers was measured before and after debonding. The resistance of the two pads and the line measured on one wafer show nearly identical results.

The electrical results for these first TSV wafers are encouraging. Resistance values are similar before and after debonding, which confirms that these slide-off debonding and cleaning processes do not generate any degradation of the device performances.

Even if a large resistance discrepancy can be measured on the wafer surface due to short-circuiting of the Al-layer on the wafer front side, the average TSV resistance values measured on all the wafers ranged from 0.83 to 1.47O, similar to resistance values measured on TSVs processed on permanently bonded wafers[3].

Conclusion

New temporary adhesive has been evaluated for its use in a temporary wafer bonding process. The adhesive meets all the requirements for bonding strength, chemical resistance, thermal stability, etc. to apply TSV process applications.

The technology, including temporary bonding and debonding, offers time and cost efficiency for further 3D packaging integration processes utilizing existing and established equipments and technologies. These results have been confirmed with the achievement of high-performance TSVs with an aspect ratio of 1:1 on 8" wafers. The results confirm that the debonding and cleaning processes do not scratch the wafer or break the ultra-thin bottom of the TSVs (only 9µm). The electrical tests performed showed that via resistance values were the same for TSVs processed using a temporary bonding layer compared to permanent bonding.

Work continues on thermal stability of the adhesive material to enable the realization of TSVs with higher aspect ratios, as well as applications using high topographies like bumps and/or chips.

References

  1. R. Puligadda, S. Pillalamarri, W. Hong, C. Brubaker, M. Wimplinger, and S. Pargfrieder, “High-performance temporary adhesives for wafer bonding applications,“ Materials Research Society Symposium Proceedings, vol. 970, 2007.
  2. D. Henry, J. Charbonnier, P. Chausse, F. Jacquet, B. Aventurier, C. Brunet-Manquat, V. Lapras, R. Anciant, N. Sillon; B. Dunne#, N. Hotellier+, J. Michailos+, “Through Silicon Vias Technology for CMOS Image Sensors Packaging: Presentation of Technology and Electrical Results;“ CEA-LETI, MINATEC, 17 rue des Martyrs, 38054 Grenoble Cedex 9, France; # ST Microelectronics, ZI de Rousset ??? BP2 ??? 13106 Rousset cedex, France; + ST Microelectronics, 850 rue Jean Monnet, 38926 Crolles cedex, France.
  3. D. Henry, F. Jacquet, M. Neyret, X. Baillin, T. Enot, V. Lapras, C. Brunet-Manquat, J. Charbonnier, B. Aventurier, and N. Sillon, “Through Silicon Vias Technology for CMOS Image Sensors Packaging,“ Proc. 58th Elec. Comp. and Tech. Conf. (IEEE ECTC 2008), 2008, pp. 556-562.

    * The system used was a fully automated EVG850TB temporary bonding platform.

    **Brewer Science’s WaferBOND HT1010 material was selected for the debonding application.[1]

    Stefan Pargfrieder graduated in technical physics at the University of Linz, Austria. He received his master thesis in collaboration with Infineon Technologies in the field of semiconductor metrology. Currently, he is the business development manager at EV Group headquarters in Sch??rding, Austria, where he is responsible for the company’s thin wafer processing, temporary bonding and debonding activities and technology development. ph: +43 7712 5311-5213; email: s.pargfrieder@evgroup.com.

    Jürgen Burggraf received his engineering degree in bionic and sensor technology. In his current position at EV Group headquarters he is a process engineer responsible for EVG’s thin-wafer processing with a focus on temporary bonding, debonding as well as processes for 3D integration. ph: +43 7712 5311-5219; email: j.burggraf@evgroup.com.

    Daniel Burgstaller received a degree in electrical engineering in 2003. He is a product manager at EV Group headquarters in Sch??rding, Austria, where he is responsible for product management with a focus on temporary bonding, debonding and lamination equipment as well as thin-wafer handling topics. ph: +43 7712 5311 5228; email: d.burgstaller@evgroup.com.

    Mark Privett has been working in the electronic materials industry in processing and applications support for the last 13 years. He is currently the product manager for bonding materials at Brewer Science Inc. in Rolla, MO. Email: mprivett@brewerscience.com

    Amandine Jouve earned a master’s degree in physics and chemistry engineering in 2003 at the National Polytechnic Institute of Grenoble (INPG - ENSEEG), and a Ph.D. in emerging lithography technologies in 2006 at the CEA-LETI research center in Grenoble. She joined Brewer Science in 2008 as a research engineer in the Advanced Materials R&D team. In this capacity, she participates in product development in the area of temporary adhesives designed for the 3DP processes. Email: ajouve@brewerscience.com.

    Nicolas Sillon received a Ph.D. from National Polytechnic Institute of Grenoble in 2001, developing a silicon micromachined mass spectrometer. In his current position with CEA-LETI-MINATEC (Laboratory of Electronics, Technology and Information) as group manager of packaging and integration, he oversees the Packaging & Integration Technologies Laboratory, focused on wafer-level technologies for MEMS packaging & 3D integration. Email: nicolas.sillon@cea.fr.

    David Henry received a technological degree in physical measurements from Grenoble University and a master’s degree in materials from the National Polytechnic Institute of Grenoble (INPG ??? ENSEEG). Currently, he is a deputy manager in charge of 3D integration in the packaging and component integration laboratory at CEA-LETI-MINATEC (Laboratory of Electronics, Technology and Information). ph: +33 4 38 78 96 88; email: david.henry@cea.fr.