The Case for Integration


Click here to enlarge image

Pete Singer Editor–in–Chief

The limits of traditional CMOS scaling are at hand, combined with an unprecedented financial crisis in the electronics industry. It’s too early to tell how it will all play out, beyond an extreme focus on cutting costs, but it’s clear that work will continue on a new generation of device architectures and electronic materials that will support a continued drop on cost per function.

As noted in the International Technology Roadmap for Semiconductor (ITRS), as traditional Moore’s law scaling becomes more difficult, assembly and packaging innovation that enables functional diversification and allows scaling in the third dimension is taking up the slack. “Assembly and packaging provides a mechanism for cost effective incorporation of functional diversification through system–in–package (SiP) technology. This technology enables the continued increase in functional density and decrease in cost per function required to maintain the progress of electronics. New architectures include printable circuits, thinned wafers and both active and passive embedded devices are emerging as solutions to market requirements. The materials and equipment used in assembly and packaging are also changing rapidly to meet the requirements of these new architectures and the changing environmental regulatory requirements.”

At the recent SEMI Industry Strategy Symposium (ISS), Jan Vardaman of TechSearch International noted that advanced packaging includes BGAs, CSPs, flip chip and wafer level packages, which accounted for 30% of the 162 billion ICs shipped in 2008. She projects that they will account for 44% of the 205 billion ICs expected to ship in 2012. Despite cuts in capex, some investment in advanced packaging will continue in the areas of: capacity for 300mm bumping and WLP; fanout WLP; 3D die stacking with through silicon vias (TSVs), and microbumps for TSV apps, she said.

3D integration and TSVs, in particular, represent a great opportunity for the semiconductor industry to continue along the path defined by Moore’s Law, without the cost — potentially huge cost — of moving to ever smaller dimensions and ever more expensive lithographic tools, such as EUV. It’s almost a given that in this economic environment, chip makers will pursue this avenue with ever greater vigor. It may be the only option left.

The beauty of 3D and TSVs is that the technologies used to etch, coat, and fill the TSVs are quite similar to those already used in volume manufacturing for front–end interconnect processes. Indeed, companies such as Applied Materials, Aviza, and Lam have introduced tools designed for TSV applications. At the same time, technologies traditional relegated to back–end have found their way to the front–end, wafer level solder bumping being a prime example.

The relationship between the chip and the package is also taking on a more important role. One of the “difficult challenges” at the >22nm node is the impact of interconnects materials and structure — including Cu and low k — on packaging. This includes: Direct wire bond and bump to Cu or improved barrier systems bondable pads; dicing for ultra low–k dielectric; bump and underfill technology to assure low–k dielectric integrity including lead free solder bump system; improved fracture toughness of dielectrics; interfacial adhesion; reliability of first level interconnect with low k; mechanisms to measure the critical properties; and probing over copper/low k. Similar challenges exist in wafer level CSP, thinned die packaging and embedded components — not to mention coordinated design tools and simulators to address chip, package, and substrate co–design.

As a result of these major “sea changes” in the semiconductor, packaging and electronics industry, we have made a momentous decision to integrate Advanced Packaging magazine into Solid State Technology. The January/February issue of Advanced Packaging will be the last stand–alone print issue; starting next month and moving forward we will be incorporating Advanced Packaging content in SST. We will also be integrating a large portion of the AP circulation into that of SST. The combined publication will go to this entire, expanded circulation list.

We hope you enjoy the new combined Advanced Packaging/Solid State Technology magazine. We will continue to maintain dedicated websites and newsletters for each. As usual, let me know what you’re thinking. You can reach me at 603–891–9217 or at