Issue



Next–Generation Lithography: EUVL readiness for pilot line insertion


02/01/2009







S. Wurm, F. Goodwin, H.Yun, SEMATECH, Albany, NY USA

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The most aggressive IC manufacturers target EUVL pilot line introduction in 2011. This goal can only be achieved if reliable commercial high–power sources become available by mid–2009, and resist suppliers working with consortia and IC manufacturers continue their progress, and if the industry is successful in developing a new business model to share the cost and risk of developing critical missing mask tools.

To enable the 32nm half–pitch (hp) node, the industry is preparing to introduce different variations of 193nm immersion double–patterning (193i DP) technologies. The choice of lithography technology for high–volume manufacturing (HVM) at the 32nm hp node is driven by the fact that extreme ultraviolet lithography (EUVL) has not matured sufficiently to be ready for manufacturing introduction.

As a result, the industry is now looking towards introducing EUVL at the 22nm hp, with more aggressive device manufacturers targeting a mid–cycle insertion between the 32 and 22nm hp nodes. Within the past year, high index immersion lithography has been dropped from stepper manufacturer roadmaps; the only viable alternatives to EUVL are costly multiple exposure techniques as the process window for 193nm water immersion double exposure is not sufficient to support robust manufacturing processes.

Flash and DRAM manufacturers’ device scaling roadmaps are the most aggressive, and those manufacturers will be the first to need lithography technology solutions that are technically mature and cost–effective. Even if potential alternative technologies to EUVL, such as nanoimprint lithography (NIL), are able to resolve their remaining technical challenges—with defects and overlay being the most important—meeting the cost challenges will be difficult. Moreover, there are concerns about how rapidly NIL will be able to ramp production to meet device manufacturers’ demands.

Although the introduction of 450mm wafers is still in the future, the industry must begin comparing the potential impact of transitioning to this wafer size against the cost effectiveness of competing future lithography technologies. Whereas a transition to 450mm would negatively impact the cost for NIL and 193i multiple patterning technologies, a single exposure technology like EUVL would benefit from it. In fact, EUVL may be the only technology to fully benefit from a 450mm wafer size transition. Arguably, however, EUVL must be manufacturing–ready for the 22nm hp node; otherwise, the industry may fall behind the timeline set in the 2008 International Technology Roadmap for Semiconductors (ITRS) [1].

For EUVL to become manufacturing–ready for introduction at the 22nm hp or earlier for a mid–cycle introduction between the 32 and 22nm hp, some key technology and business challenges need to be aggressively pursued to enable EUVL pilot line operation in 2011.

Status of EUVL technology

At the 2008 EUVL Symposium [2], EUV sources remained the main concern for the third consecutive year. EUV masks and resists swapped rankings since EUV mask technology is now considered more critical than resist, due to the progress in EUV resist development over the past two years. Specifically, EUVL technology and business development must demonstrate the following:

  • Long–term source operation with 100W at the intermediate focus (IF) and 5MJ (megajoules) delivered per day
  • Defect–free masks through lifecycle and inspection
    eview infrastructure
  • Resist resolution, sensitivity, and line–edge roughness (LER) targets met simultaneously.

EUV source

For several years, the EUV power requirement that exposure tool suppliers have agreed upon has remained constant at 180W at IF. This specification is based on a resist sensitivity of 10mJ/cm2; additionally, the 180W must be delivered at the IF within a 2% bandwidth window centered about the 13.5nm wavelength. Radiation produced by the plasma source outside the 2% bandwidth (i.e., out–of–band [OOB] radiation) needs to be suppressed because OOB radiation reaching the resist could diminish image contrast as resists tend to be sensitive to such radiation.

Integration of medium power level source collector modules (SoCoMos) that can reliably support ~50W at the IF over extended operating periods remains the key challenge delaying the adoption of EUVL. The industry has developed two EUV source technology choices over the past decade: discharge produced plasma (DPP) sources and laser produced plasma (LPP) sources.


Figure 1. Usable output power at the IF as reported and projected by source suppliers [3, 4].
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Figure 1 shows the progress reported by source suppliers of usable EUV power output delivered at the IF. The numbers are much lower than the projected collectable power numbers of 50W, and greater at IF than suppliers reported in the past. This reflects the difficulty of building integrated sources that include efficient collection of EUV light, effective debris mitigation, and possibly spectral filtering, all of which tend to reduce the actually achievable power output at IF.

DPP sources currently in use in alpha tools support operation at a few watts of EUV power at the IF. This is significantly lower than the ~200W at IF level that will be needed in manufacturing tools. Scaling DPP sources to this higher power level while maintaining high reliability and uptime will be challenging. Generating higher EUV power levels at the source point seems possible; however, extracting the generated EUV power with collectors and debris mitigation devices engineered to withstand higher thermal loading is proving to be more difficult.

The challenges DPP sources will have to meet as power is scaled up are greater than those restricting LPP source output. Also, the ultimate power level that can be produced by LPP sources will likely be higher than that for DPP sources. This becomes important if one looks beyond the first generation of EUVL HVM tools for which power requirements could scale to 500W at IF and higher.

While scaling technology to higher power requirements is less of an issue for LPP than for DPP technology, a fully integrated SoCoMo has not yet been demonstrated. Achieving the required power at IF, efficiently collecting EUV photons, and solving the debris mitigation problem are also seen as key challenges for LPP. In addition, increasing the power of pump lasers and cost–of–ownership (CoO) are other critical issues. Clearly, CoO is a more immediate concern for LPP sources because they have been selected for use in beta–type exposure tools and will likely be used in the first EUVL production tools.

The current projections for 300???500kW of electrical input power is an environmental concern and may drive the need for more efficient EUV sources. Developing sources with greater efficiency will be more difficult for DPP than for LPP. LPP–source efficiency can dramatically increase if diode–pumped laser modules can be used, but improving the efficiency of an electrical discharge source is more difficult.

As Fig. 1 shows, suppliers of DPP and LPP sources projected a dramatic increase in output power at IF by the end of 2008. Early adopters of EUV technology expect a wafer throughput of ~50wph for EUVL beta tools in a pilot line environment. This will require a power level at IF of ~100W, which is significantly higher than the current ~4W level that has been demonstrated for long–term operation of LPP development sources [5]. However, there is confidence that power at IF close to the required level can be achieved by mid–2009. LPP EUV sources for beta tools have been moved out to the supplier R&D space and into manufacturing bays with commercial sources being targeted for delivery in early 2009 [6].

Understandably, EUV sources readiness is still seen as the major risk to the introduction of EUVL. EUV source challenges must be addressed soon, or EUVL will never be introduced into pilot lines. Once sufficiently mature sources enable pilot line introduction, mask yield is expected to quickly become the most important issue for EUVL.

EUV mask

In a recent industry survey, SEMATECH assessed the perceived readiness of the EUVL mask infrastructure to support mask pilot lines [7]. Respondents were asked to rate their perception of EUV mask infrastructure readiness for pilot line manufacturing in 2010???2012. As shown in Fig. 2, a significant portion of the mask infrastructure is still not perceived as ready to support mask pilot line operation in the targeted timeframe. Notably, many of the deficient areas support defect inspection capabilities for substrates, mask blanks, and patterned masks and full–field and small field actinic inspection.


Figure 2. Mask infrastructure readiness survey results. A 25% threshold of respondents was required for a color code to be shown for a given category.
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Bridge solutions are available for key areas that are not yet ready, or current capabilities may be sufficient to support the initial pilot line start–up. Patterned defect inspection is one of those areas. Ultimately, an actinic patterned defect inspection tool will be required, but initially, the current inspection technologies and printing inspection can support EUV pilot line introduction. For other areas, such as fab defects, insufficient data is available today to understand how critical the capability will be.

The situation is very different for mask substrate and blank inspection, and to some extent, for actinic aerial imaging tools. Progress has been excellent in reducing mask blank defects added during the multilayer deposition process. Progress has also been made in reducing the bump and pit defects levels of the starting mask substrate. However, defect reduction on substrates has lagged compared to defect reduction efforts in multilayer deposition.

The best mask blank defect level that can be achieved is limited by the defect level of the incoming substrate as most of these defects directly translate into mask blank defects. Although the total number of defects found on the best substrates is not high, the multilayer deposition process decorates defects that are too small to be detected by the substrate inspection tool, but are found by the mask blank inspection tool after the multilayer deposition, and will likely image during exposure.


Figure 3. First and second generation tools capable of inspecting both substrates and EUV mask blanks. Further improvements in sensitivity will require separate inspection capability for substrates and EUV mask blanks due to multilayer damage considerations.
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Clearly, a much improved substrate defect inspection capability is needed that enables detection of defects down to a 15???20nm polystyrene latex (PSL) size equivalent. As shown in Fig. 3, for the first two EUV substrate and mask blank tool generations, the same tool has been used to inspect substrates and mask blanks. Improving the sensitivity of the inspection tool usually focuses on reducing inspection laser wavelength and increasing laser power. While this approach is still feasible for substrate inspection, due to potential damage to the multilayer, it is not a strategy that could support mask blank inspection.

Current inspection tools already operate close to the damage threshold of the multilayer stack. Defect detection is essentially a photon–counting process that requires a certain number of photons to achieve the required signal–to–noise (S/N) ratio. To maintain that S/N ratio, the number of photons that contribute to the signal must stay the same. As each photon carries higher energy due to decreased wavelength, the total energy deposited into the multilayer increases, which essentially limits the possible reduction in inspection wavelength for mask blanks. In addition, the shorter the wavelength, the more surface–sensitive the inspection becomes because of decreasing skin depth. Therefore, the next generation of mask blank inspection tools will require EUV wavelength operation to deposit less energy in the distributed Bragg reflector of the multilayer.

The industry needs a next–generation substrate inspection tool by late 2009/early 2010, or the rate of progress in reducing substrate defects will not accelerate as required to meet the mask blank defect pilot line goal 0.04 defects/cm2 at 18nm in 2011. Procuring a new tool generation is more of a business challenge than a technical one. Only one new substrate inspection tool will initially be required to support the mask blank development roadmap. Although alternatively, non–optical methods could be used for defect inspection as a bridge, they would have very low throughput and not be able to support the volume of substrates requiring inspection.

Likewise, the next generation of mask blank inspection tools are needed by 2011 to support the final development roadmap requirements to meet HVM defect specifications, which typically follow two years after EUVL pilot line introduction. EUVL mask blank suppliers will need these tools to provide certified blanks with essentially no defects. These inspection tools must also map the locations of any remaining defects so that mask manufacturers can subsequently use defect mitigation methods to obscure those defects that could print during exposure. To verify that mask blank defect mitigation is successful and that the repairs made to patterned mask defects are non–printable, mask shops will need EUV aerial imaging tools. Although the market for aerial imaging review tools is greater than for actinic blank inspection tools, the total number is still low. Developing and building these tools is again more of a business than a technical challenge for tool suppliers.

A new business model is required to enable the EUV actinic inspection and aerial imaging tools. First, by targeting a joint platform approach for inspection and aerial imaging tools, the industry will not have to front the cost for the development of two completely different platforms. Second, by sharing the risk and cost of the development effort between all end customers and the supplier, the initial development cost incurred by the supplier can be lowered. If possible, the end customers can recover their respective development investments through negotiating a tool pricing that will take into account their cost share of the development.

If the next generation of substrate and mask blank defect inspection tools becomes available in late 2009 and 2011, respectively, then the industry can be confident that mask blanks with sufficiently low defect counts will be commercially available to support the mask yield requirements of pilot lines and later on of HVM fabs for the 22nm hp node.

EUV resist

EUV resist development has made impressive progress over the past two years. The resolution of current resist platforms has been consistently underestimated by the industry. Only a few years ago, there was significant concern that the resolution of chemically amplified resists (CARs) could hit a brick wall at ~35nm hp. Now, as shown in Fig. 4, CAR platforms have recently broken the 22nm hp imaging barrier and demonstrated image modulation down to 20nm hp [8].


Figure 4. EUV CAR platform breaking the 22nm hp imaging barrier and demonstrating excellent contact hole resolution at 30nm. Images were recorded with the SEMATECH EUV MET at the Berkeley Advanced Light Source (ALS) Lab.
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Recently, the resist calibration that had been used for many years to determine resist sensitivity was found to be off by a factor of 1.9??. Resist photospeed is therefore ~ 1.9?? higher than assumed, which brings resist sensitivity much closer to the 5???10mJ/cm2 range on which the current source power assumptions for a 100wph throughput EUVL exposure tool are based.

In addition to sub–22nm hp imaging of dense lines and space patterns, EUV CAR platforms have demonstrated excellent contact hole imaging. Figure 4 shows an example for 30nm contact hole imaging that was recorded using SEMATECH’s EUV micro exposure tool (MET) at the Berkeley Advanced Light Source Lab. Sub–30nm contact hole resolution with good isolated/dense contact hole bias has also been demonstrated on EUV alpha tools [9].

While the results for resolution and sensitivity are encouraging, the resist parameter that has seen limited improvement is line width roughness (LWR). Meeting the 1.7nm/1.1nm LWR specifications of the ITRS for the 32/22nm hp nodes will be extremely challenging. The best resist available today can image down to 20???22nm using a 0.3 NA projection optics and rotated dipole illumination at sensitivities close to 10mJ/cm2, but the resulting LWR is in the 5???6nm range.

To support the early introduction of EUVL between the 32 and 22nm hp nodes, resist suppliers must focus on engineering resists that meet very specific requirements, including a fast resist with high resolution and moderate LWR ~4nm) that can support DRAM and Flash applications for the near future, but allow the moderate LWR to be improved through post–processing of the resist or through LWR–reducing etch processes. In the near–term, MPU gate–level processing will require a slower resist with higher resolution and a better LWR to meet the 1.7nm specification required by MPU gate–level processing.

Parallel to this, a more fundamental approach is needed to enable break–through developments. New platforms or chemistries must be pursued to meet LWR requirements for future patterning nodes. This includes a better understanding of EUV resist exposure mechanisms. Initial results from SEMATECH–supported work on increasing the quantum yield of resists to >4 have been encouraging [10].

Resist break–through development, which can significantly shorten the time to develop new platforms, will only be possible if resist suppliers gain a better understanding of energy transfer processes in resists. Controlling resist component distributions on the pixel level to improve the targeted resolution, to keep excitations localized, and to restrict decay channels is different from the industry’s usual trial–and–error approaches. However, this is the only way to enable pattern transfer that meets the ITRS specifications for the sub–22nm hp technology nodes.

Conclusion

The first EUV alpha tools support manufacturability assessments and integration learning by device manufacturers using EUVL for critical layer printing. However, for EUVL to be successfully introduced into pilot lines in 2011, several key challenges still must be addressed. Foremost is the need for commercial versions of critical mask tools, which are indispensable to enabling EUV mask yields that support EUVL pilot line introduction.

Acknowledgments

The authors would like to acknowledge their colleagues in SEMATCH’s EUV Strategy and Mask Strategy programs: Chawon Koh and Sungmin Huh (Samsung); Kevin Orvek (Intel); Abbas Rastegar, Pat Kearney, Jaewoong Sohn, and Andrea Wuest (SEMATECH).

References

  1. International Technology Roadmap for Semiconductors, http://public.itrs.net/.
  2. 2008 International Symposium on Extreme Ultraviolet Lithography, September 28 October 1, 2008, Lake Tahoe, California; http://www.sematech.org/meetings/archives.htm#litho.
  3. 2008 SEMATECH EUV Source Workshop, May 12, 2008, Bolton Landing, New York; http://www.sematech.org/meetings/archives.htm#litho.
  4. International EUV Intitative Source Technical Working Group, October 2, Lake Tahoe, 2008, California; www.ieuvi.org.
  5. D.C. Brandt et al. in ref. #2.
  6. D.C. Brandt et al., Laser Produced Plasma Source System Development, SPIE Lithography Asia, November 2–4, 2008, Taipei, Taiwan.
  7. International EUV Intitative Mask Technical Working Group, October 2, Lake Tahoe, 2008, California; www.ieuvi.org.
  8. C. Koh et al. in ref. #2.
  9. H. Meiling et al. in ref. #2.
  10. R. Brainard et al., J. Photopolymer Sci. Tech. 21 (3), 457 (2008).

Stefan Wurm received his doctorate in physics from the Technische Universit??t München, Germany. He is a principal member of technical staff at Advanced Micro Devices and the associate director of lithography at SEMATECH, 255 Fuller Road, Albany, NY 12203, USA; email stefan.wurm@sematech.org.

Frank Goodwin received his masters in electrical engineering from Cornell University. He is a Senior Member of Technical Staff at SEMATECH.

Henry Yun received his PhD in materials science and engineering from the U. of Washington. He is a senior staff engineer at Intel Corporation currently on assignment to SEMATECH as mask strategy program manager.