Embedded Passives, RF Design


Overcoming Mixed-Technology Design Challenges


Today, wireless system designers are driven to find low-cost ways to implement higher performance and greater functionality into smaller packages by combining digital, analog and radio-frequency (RF) technologies onto a single PCB. To create these mixed-technology designs, engineers in different disciplines must work together to reduce their time-to-market by developing designs concurrently in a standard process involving design capture, layout, verification, and release-to-manufacturing.

One way for designers to incorporate the various technologies into their RF designs is by fabricating passives, such as resistors and capacitors, into PCBs during the board fabrication process. Using this technology, passives can be placed directly below active devices (ICs). The shorter distance between the passives and active components reduces the parasitics associated with surface mounted passives, resulting in better signal transmission and less cross talk. RF designers, especially, require special transmission line components and a flexible design environment to solve their design trade-offs in high-density, multilayer packages, which are generally not supported in standard PCB tools.

This article discusses general design challenges facing mixed-technology RF designs, as well as the more specific challenges of incorporating embedded passive technology into these designs.

RF Design Challenges

New applications for the wireless Internet (WiFi) are being integrated into multi-band handsets with stringent standards for universal mobile telecommunications systems (UMTS), Bluetooth, and global positioning systems (GPS). These applications are changing the way major telecommunications companies do business. For instance, many firms are turning to OEMs that specialize in wireless product design using sophisticated electronic-design-automation (EDA) tools. Designers integrating mixed technologies on the same PCB must face the challenge of higher frequencies, embedded passives, coupling parasitics, modeling interconnects, wider bandwidths, and high-speed digital signal processors (DSP) (Figure 1). RF designers, on the other hand, demand parameterized distributed elements and a flexible design environment.

Figure 1. Mixed-technology design in telecommunication systems.
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Operating in an environment with electrical disturbances, wireless systems are often portable. They demand compact size, low weight, and low power consumption. But when microwave components are placed close to each other, tight integration and special design considerations become necessary. This problem arises in two-way pagers, cellular phones, personal communication systems (PCS), and wireless local area networks (WLANs). As the drive toward added functionality in an ever-shrinking package continues, the size of components and the distance between them must shrink.

Mixed-technology design implementation involves placing circuit elements carefully to reduce design size, while satisfying circuit isolation and mechanical constraints. This includes consideration of analog/mixed-signal design tools for the baseband portion of the wireless communication system, as well as hardware and software co-simulation. Accurate interconnect modeling, or extracted parameters from an electromagnetic simulation, can provide necessary information about the RF section. RF EDA tools use an automatic shape generation algorithm for layout creation of RF blocks, including the arbitrary placement of user-defined parametric shapes on inner PCB layers. This process creates and optimizes buried components. Such RF-layout automation capabilities extend the power of standard place-and-route tools beyond existing digital and analog functionality.

With higher integration and larger RF blocks, it becomes difficult to create RF layout with standard schematic-driven-layout (SDL) processes. Today, the physical model or layout dominates the design-creation process. Sophisticated PCB tool vendors have expanded the limitation of the SDL process. RF distributed elements are now placed and connected in layout, and changes are back annotated into the schematic.

To conquer high-density RF designs with many buried components, it's not enough to place parameterized distributed elements in layout. Free-form component structure editing, while maintaining component information of the associated copper shapes, becomes mandatory. Advanced technologies for component modifications must be integrated into a powerful PCB routing environment. That environment includes traces with respect to RF design requirements (e.g., the automatic generation of mitered and curved bends).

RF subcircuits containing distributed components naturally lend themselves to being incorporated into inner layers of the board. Passive components used in these RF circuits can also be embedded on the inner layers using various technologies.

Embedding Passive Components

Passive components are becoming a significant portion of the total number of components used in RF applications, where most of the components are resistors followed by capacitors and inductors. Passive components have not kept up with ever-shrinking ICs, and peripheral passive components are not as functionally space efficient as ICs and are one of the major roadblocks in increasing the functional density of mobile electronic systems. The need for greater functional density is forcing designers to look at creative packaging alternatives. If the historical rate of passive component density continues, by 2010 it is reasonable to expect passive component density of 20 to 30 passives/cm2. Embedding passive components in PCBs is an enabling technology that provides PCB manufacturers with a process to make boards smaller, cheaper and faster. To fit more ICs and passive components into a design without increasing size, methods to bury some components, specifically passives within innerlayers of multilayer PCBs, are being explored (Figure 2). Embedding passives into the board substrate provides potential advantages for many applications. The generally accepted advantages include:

  • Increased circuit density by saving space on the substrate;
  • Decreased product weight;
  • Cost reduction through increased automation;
  • Improved reliability by eliminating solder joints;
  • For RF applications, the need to electromagnetically shield the board may be reduced by embedding passives;
  • Reduced routing (nets and vias) associated with discrete resistors that are replaced by embedded resistors fabricated in series with the nets they are attached to on the wiring layers.

Embedding Resistors

Two technologies are used for embedding resistors: thin film and thick film. Thin film technology, which is a subtractive process from the manufacturing point of view, involves etching out the conductive layer to expose the resistive foil underneath. Thick film is an additive manufacturing process, in which the resistive material is printed on the conductive layer to create the resistor.

Figure 2. Embedded components within a PCB.
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Thin Film Resistors. A bi-metal foil*, copper foil with a thin plating of a nickel alloy, becomes the resistor element (Figure 3). The nickel alloys are NiP, NiCr or NiCrAlSi, which are deposited on the copper foil using a sputtering process. Then, by etching the copper and the nickel, patterns of nickel resistors with copper terminations are formed. These are laminated into an internal layer. The bi-metal foil has a limited resistance range: 25 to 250 Ω/square. But it is possible to make higher-value resistors by making long meander/serpentine patterns (high length to width). This has the drawback of spending a lot of space within the PCB layer. All the thin film foil resistor types have one common constraint: it is necessary to create resistors on separate layers with different sheet resistivities if a wide range of resistor values is needed.

Figure 3. Ohmega-ply resistor material.
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Thick Film Resistors. Polymer thick film (PTF) materials provide highly reliable PTF embedded resistor technology. PTF resistor technology allows for multiple materials to be printed on the same layer, thereby covering resistors with values from as low as 20/Ω to as much as 10/MΩ. PTF-embedded resistors are printed either directly on etched copper terminations or on screened silver paste terminations. Interposing screened polymer silver paste between the copper and resistor results in highly reliable and stable resistors because it reduces corrosion at the copper/carbon ink interface. The silver paste screening step determines resistor length, and space must be allowed for misalignment of the silver paste with the copper.

Embedded passives eliminate component and placement costs. The incremental cost of the embedded resistor is almost independent of the number of resistors printed. Embedded resistor tolerances depend on a large number of factors. A wide range of target resistor values is a greater challenge than a narrow range. Sheet resistance variation due to material non-uniformities, typically, is an important factor in resistor value variation across different instances of resistors. PTF resistors can be laser-trimmed to 1% tolerances without any adverse effects on long-term resistor stability or reliability.

Embedded Capacitance

The most common method for using embedded capacitance involves a concept called distributed or plane capacitance. The starting material is a copper-clad laminate with a thin dielectric layer. This is fabricated into a power/ground pair. The thin dielectric results in a close spacing between power and ground. This capacitance can be accessed with conventional plated holes. Plane capacitance is valuable in high-frequency situations where the inductance of conventional discrete capacitors increases.

Discrete capacitors can be embedded by printing a high dielectric constant paste onto one plate, curing it, and then printing or plating another plate on top. These have high dielectric constants, and the high capacitances of densities of 100 to 180 nF/in.2 are possible.

Layout-driven Design

The ability to generate geometries for the embedded resistors, based on input parameters, allows these components to be directly added into the design in the layout tool. Figure 4 shows the palette in layout tool that allows addition of both thick and thin film resistors. Resistors can be connected to other components on the PCB by using the 'CONN' icon. The 'DISCONN' icon allows the removal of existing connections. Connections made are displayed as guides in the layout editor, and can be routed.

Figure 4. Layout-driven design for embedded passives and RF components.
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The changes to the design done on the backend in the layout tool are back-annotated into the schematic when the design changes are committed to disk. The newly added resistors, with the appropriate connections, are shown on the schematic as they are implemented in the layout. The resistor instances themselves are placed in the top left-hand corner of the schematic, and can be subsequently 're-placed' by the user.

Figure 5. Buried resistor in layout editor.
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The geometry for a thick film resistor is shown in Figure 5. This is controlled by parameters that can be changed by double clicking on the resistor instance either on the schematic or in the layout tool. It is possible to add new resistor instances using the palette, or clone existing resistors in the design using the dialog box shown in Figure 4. A routing 'keepout' is added between the pads, because the resistor material is not part of a signal layer. The overlap of the pad with material and its extension beyond the resistor width is also controlled with parameters.

Bulk Manipulation and Optimization

Multiple buried resistors can be manipulated simultaneously using a buried resistor spreadsheet. This can be accomplished on the schematic, and it shows all resistors in the currently active schematic sheet. In the layout tool, this spreadsheet shows all the resistors used in the entire layout design, allowing macro changes, such that multiple resistor instances can be simultaneously changed. When optimizing, the system chooses the minimum area for each resistor value/material definition combination.

Figure 6. Bulk resistor spreadsheet.
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The tools also allow exporting the resistors in the design to an MS Excel comma-delimited file. Any changes can be imported back into schematic or layout tools. The same process can manipulate PTF resistor material definitions. Multiple buried resistors can be changed simultaneously using a buried resistor spreadsheet (Figure 6).


For a complete list of references, please contact the author.

*Ohmega Ply.

Loy D'Souza, senior R&D engineer, may be contacted at Mentor Graphics, 5030 Bradfford Dr., Bldg. 1, Suite 130, Huntsville, AL 35805; (256) 864-3821; e-mail: