Impact of Flip Chip on Flex Processes
Best-In-Class Product Density at Minimum Cost and Maximum Production Rates
BY FRITZ BYLE
Mounting of flip chip components directly to flexible circuits is rapidly becoming a mainstream process for the construction of some classes of electronic devices. The use of flexible circuits enables lower product weight and size, and eliminates multiple substrates and the associated cost and reliability risk of interconnections. The flex circuit also enables product shapes that would otherwise be difficult or impossible to produce economically. without the use of a flexible substrate.
Flip chip on flex (FCoF) is becoming an attractive method to mount small- to moderate-size analog and digital die, reducing the packaging cost and providing benefits in electrical performance. High-density flex circuit technology developed for chip scale packages (CSPs), based on flexible substrates, will make its way to the general flex substrate marketplace. This high-density routing capability, coupled with an extremely light weight and mechanical flexibility, will make the flex circuit a formidable player in the electronics marketplace. Its impact on the packaging world will drive significant volume in wafer-level CSPs, as well as true flip chip. With packaging costs minimized and many costly interconnects and multiple substrates eliminated, total product costs will fall and functionality can increase. One problem, however, is the mounting process for wafer-level CSPs and flip chips. An underfill step is required, and although capillary underfills provide robust reliability, the process is less than desirable economically.
The most economical process for mounting FCoF uses no-flow, or reflow encapsulant (RE) underfill technology. Line throughput increases of >30%, along with reduced line footprint and work-in-process have been demonstrated in high-production environments. The process for FcoF using no-flow consists of dispensing underfill, placing die and processing. Soldering is performed concurrently with other devices that are present. Underfill may also be pre-applied to the die, although this approach is in the development stages.
Just as understanding SMT processes is a key concern for manufacturers of leaded and discrete components, understanding the no-flow process is critical for advanced package manufacturers. Some of the technology developed for final assembly will make its way back into packaging. No-flow underfills will evolve to displace capillary underfills in some packages. This article presents the process aspects of FCoF mounting using the RE-based process, in the order of process flow.
Die size, initial and collapsed bump height, bump count, and flexible circuit layout are all factors that affect the amount of encapsulant required. There must be enough encapsulant to wet all of the bumps and lands prior to reflow, but not so much that a too-large fillet is produced. A fillet that is too large can result in reduced process yield (die float) and reduced reliability (increased stresses). Figure 1 (on the left) shows a substrate prior to assembly, with the RE dispensed. Figure 1 (on the right) shows the target post-reflow condition. Note the moderate fillet size.
Figure 1. Dispensed underfill and assembled chip.
Dispense quantities usually can be predicted by a spreadsheet to within ±20%. The tolerance for dispense quality usually is ±20 to 25%, greater for very small die, and less for larger die. Figure 2 shows the relationship between die size and material volume at a constant standoff of 100 µm. The tolerance band is shown in green. For die greater than 5 mm2, the acceptable tolerances are ≤10%, and it is more difficult to model the required volume. Dispense must be finalized during the initial process set up. For small die sizes, modeling volume is easier, but actually dispensing and verifying the volumes is more difficult. For deposit weights greater than 2 mg, using a 5-place lab balance can provide a capable means for verification. For smaller deposits, however, gage R&R studies show that optical methods are superior.
Figure 2. Dispense quantity and tolerance relationship.
Dispensing can be achieved using either Archimedes screw dispense pumps or by "jetting." Screw pump dispensing performance is dependent on the equipment used. For deposit weights less than 2 mg, the needle size required becomes small enough that dispensing is difficult. Wetting of the external surface of the needle also can be a problem, as can dripping or pullback caused by inadequate sealing/seating of the screw during the period between dispense cycles.
Screw pump dispensing equipment is well understood, and has a large installed equipment base, although it is not capable of achieving adequate CpK for die sizes less than about 2.5 mm × 2.5 mm. Jetting the RE materials has been demonstrated, and provides advantages of speed and tight volume distributions — even for dispense quantities of less than 1.0 mg. Jetting is just being implemented for dispensing RE materials. It will see significant interest as die sizes shrink. This technology also avoids needle clogging and wetting problems. The economic and technical benefits of jetting will drive the required process development work for product implementation.
The RE provides the same functionality as the TSF and capillary underfill. The placement equipment is relieved of the task of fluxing the die, significantly improving throughput in the placement cell. Qualifying a single material eliminates the problematic flux-underfill interaction. Qualifying a compatible TSF and underfill is a major challenge.
Placement into the RE is similar to placement using tacky flux. Placement forces may be slightly higher, and a short hold time is occasionally beneficial. When a hold time is required, it usually is less than 250 ms. As with TSF, die will self-center if the placement accuracy is not too far off. The bump must contact the top of the land. If placement is off so that the bumps slide off the edge of the lands, centering may not occur.
The RE is forced out to the chip edges by compression flow as the chip is placed. As this happens, small gas bubbles may be incorporated into the RE as the material flows around bumps and over substrate topography. This is not of concern, because the RE will absorb these small voids during heating.
There are different concerns in the soldering process when using RE, as opposed to tacky flux. With RE, the substrate is encapsulated during the soldering process so that any gas generated by the substrate (or die) during reflow has nowhere to go except into the RE. The RE can absorb some gas during heating, but the presence of large amounts of gas will result in large voids in the RE. Large voids can lift the die, preventing soldering. In less severe cases, they may impact reliability, so large voids are not allowed.
Figure 3. Analysis of outgassed species.
The substrate typically is the source of the evolved gas, although water vapor makes up some of the outgassed material. In many cases, however, significant amounts of higher boiling materials also are present and are not removed by the typical moisture bake-out regimen. These compounds typically are organic (carbon) compounds, and can be solvents, plasticizers, decomposition products, or unreacted chemistry from adhesives. This list is not comprehensive. Figure 3 shows the results of a recent analysis of a substrate before and after reflow. The plot is a FTIR scan, repeated at intervals during sample heating. The sample was taken from room temperature to a peak temperature of approximately 240°C. Peak 1 in Figure 3 corresponds to water; peak 3 corresponds to CO2; and peaks 2, 4 and 5 are organic materials. While the water was drastically reduced in the reflowed sample, most of the organic material was not as drastically reduced. The organic materials come out later, indicating higher boiling points or that they are decomposition products. The apparent reduction in CO2 may not reflect reality. Stray sources of CO2 may account for the difference. When outgassing is controlled, mounting with RE results in void-free, fully encapsulated chips with well-formed fillets. Unlike mounting with TSF, processing with RE can be performed in air, along with SMT components, assuming an air-compatible, lead-free solder paste for the SMT.
Visual inspection of flip chip devices assembled with RE technology is nearly impossible. X-ray inspection is necessary to assess soldering performance, and CSAM is required to determine the size and location of any voids. Cross sectioning can be used as a destructive alternative for both of these techniques during initial process optimization.
Inspection of flip chip joints by x-ray requires a relatively high-magnification x-ray system. The low x-ray density of FCoF assemblies does not require high-energy x-rays, however. Acceleration voltages of 50 to 70 kV are adequate. This enables inspection with benchtop x-ray systems for low volume or low sampling rates from high-volume lines. The linear magnification should be at least 25 to 50X for adequate visual assessment of soldering performance. Figure 4 shows an example of an assembled chip with good soldering; note the evidence of wetting along the traces. As in Figure 1, there is no soldermask to prevent wetting. The four central bumps have no trace associated with the pad, so no wetting is visible from the top. Note the sharp edge and circular shape of these bumps. Unsoldered bumps have this same appearance, even though there is a trace associated with them. To assess wetting to pads without traces, an oblique angle is required. A noncircular pad can enable x-ray verification of wetting since the bump will become elongated. X-ray analysis is compatible with eutectic Sn-Pb and lead-free (SnAg, SnAgCu) solder alloys.
Figure 4. X-ray analysis of attachment.
CSAM analysis of FCoF assemblies is straightforward. The flip chip dice transmit ultrasonic energy without significant scattering, and high frequencies are not necessary because the voids of interest are large (> 50 µm in diameter). Since the voids take most of the die standoff distance, missing them by looking at the "wrong" interface is unlikely.
Figure 5. CSAM analysis of attachment.
Figure 5 shows CSAM images of mounted die. White areas represent higher reflection (usually voids), but solder joints also appear white in these images. The images represent the same product analyzed above for outgassing. On the left is a die mounted to a pre-reflowed substrate. On the right is a die mounted to an as-is substrate. Note that the pre-treated sample shows less voiding. Most of the white area represents solder joints.The non-treated substrate (on right) has one large void. This void and the smaller voids around the solder joints are a result of volatile organic compounds present in the substrate. These compounds are not removed by standard moisture bake-out regimines, but only by higher-temperature treatments. The long-term solution to this problem is to define test methods and specifications to allow substrate suppliers and users to agree upon and monitor substrate outgassing. These specifications do not exist; however, the coupled TGA-FTIR test method is well understood and readily applied to the problem. Some OEMs and their CEM partners have addressed this issue internally and achieved repeatable, void-free assembly.
The inevitable transition to lead-free, coupled with continued downward pressure on product cost, is further compounded by ever-increasing product functionality and product size reductions. Flip chip (or wafer-level CSP) mounting on flex is a logical way to provide best-in-class product density at minimum cost, at maximum production rates. Processing of flip chip concurrently with discrete and passive devices in a single step is necessary to maintain lowest cost.
The mechanical properties of no-flow underfills are not equivalent to capillary-flow materials. Due to process requirements, and the differing reliability demands and failure modes of FCoF, fillers are present at lower concentrations or are not present at all. CTEs are therefore higher, and elastic moduli are somewhat lower. This should be considered when designing packages destined for FCoF assembly.
RE, or no-flow technology, enables a streamlined production process, using processes that are well known and characterized. The evolution of no-flow underfills will continue, because they are optimized to meet the reliability demands of FCoF. As the no-flow market matures, these materials also will have an impact on packaging by replacing capillary underfill in some package applications.
Outgassing from organic material in packages and substrates is a major factor that needs to be managed for successful implementation of RE technology for FCoF. Analysis of outgassed materials by coupled TGA/FTIR or coupled TGA/mass spectrometry can help to identify offending compounds. Component and substrate suppliers must be aware of outgassing as a problem, and address it in their materials specifications and manufacturing processes. No-flow materials need to evolve to be as tolerant as possible off low to moderate levels of outgassing.
FRITZ BYLE, senior advanced products engineer, may be contacted at Kester, 515 E. Touhy Ave., Des Plaines, IL 60018-2675; (847) 699-4637; e-mail: email@example.com.