Equipment for Advanced Packaging
As an enabling technology, automated microelectronic and photonic manufacturing equipment is the engine that propels today's product concepts from the laboratory into large-scale commercial, military and industrial prominence. Wafer fabrication equipment is driven by widely standardized feature-width silicon technology nodes and wafer sizes. Assembly and packaging equipment, especially in the realm of advanced packaging, is driven by specific packaging formats that are not standardized. In the leading edge of the market, emerging packaging methods and novel materials provide the impetus for innovative packaging and interconnection processes and equipment.
Although wafer fabrication and assembly and packaging equipment are classified as semiconductor capital equipment, there are profound differences in the markets and economics of each. The situation in assembly and packaging equipment design is exacerbated by its own set of factors. The number of total customers and applications and form factors for assembly and packaging equipment is more than 10X higher than for wafer fab equipment. Despite this, total sales of assembly and packaging equipment (less mold, trim and form) accounts for less than 10 percent of the total semiconductor equipment sales, although the unit volume is much higher. Package cost does not mirror the traditional die cost reduction trend.
At the same time, the boundaries between semiconductor, packaging and system technologies are beginning to merge. Package design is driving greater complexity in design process and tools and for timely and accurate materials information.
Physical, thermal, electrical, mechanical, assembly and manufacturability considerations, in addition to price and time to market challenge package designers. These same issues face the equipment designers who must not only satisfy current requirements, but also anticipate capabilities that will be required in equipment platforms in the future. Machine architecture and functional advanced have been enabled by large area air bearings, accurate linear motors and encoders, voice coil drives, powerful machine software and rich graphical user interfaces. With these tools, it is important for equipment suppliers to try to understand their customers' processes to an even greater degree than their customers.
Trends to Watch in Advanced Packaging
Cost of Ownership. Productivity per square meter of factory floor space will drive technology trade-offs for all market segments.
Versatility. Highly flexible, multifunction automation tools will be favored. To leverage silicon technology effectively, designers must use affordable assembly and packaging solutions that are relatively independent of pin count. Thin die, stacked die, very small and very large die with high bump densities will require die attach equipment capable of multiple material presentation options with flexible, rapid changeover between product types.
Capability. Micro- and nano-positioning equipment will support increasing pin counts, while die sizes are expected to remain fairly constant. The expected reduction of flip chip bump pitch from its current 150 µm to 100 µm in the next 5 years will result in significant scaling down of under bump metallization via size, together with bump size and height. As an alternative to traditional Pb-Sn solder joints, Au bumps with a coplanarity of 2 µm can be produced in one pass on a wire bonder. Even though it appeared that wire bond pitch was approaching a physical limit, 20-µm pitch is on the roadmap. This will drive reduction in wire size, capillaries and innovative solutions for mold sweep and signal integrity, not to mention the need for equipment operators with exquisite vision, patience and fine motor skills.
Thermal Solutions. Over the next 5 years, cost per pin is expected to decline by more than 35 percent, while power dissipation (W/mm) on a constant size die will increase by 45 percent (2003 ITRS) Dissipating heat, while maintaining satisfactory junction temperatures in ICs, power transistors and solid-state lasers will require innovative heatsinking techniques, because engineers predict energy densities at the device surface will approach 60 W/cm2. Junction temperatures must be regulated to attain higher operating frequencies and increased reliability. In the specific case of optoelectronic packaging of laser diodes, device temperature greatly influences operating frequency and long-term reliability under austere service conditions, hence the die attach step that controls the device heatsinking is critical.
As the enabling technology that thrusts today's product concepts from prototype into large-scale commercial, military and industrial prominence, automated microelectronic and photonic manufacturing equipment and their designers are motivated to solve the problems faced by the packaging and process engineer.
BRUCE W. HUENERS, vice president of Marketing, may be contacted at Palomar Technologies, 2230 Oak Ridge Way, Vista, CA 92081; (760) 931-3600; e-mail: email@example.com.