Design for Reliability of Stacked Die CSPs




Chip scale packages (CSPs) are in high demand for portable and handheld electronic applications, such as cell phones, notebook PCs and PDAs. CSPs provide a small footprint, are lightweight and offer high electrical performance. At the same time, stacked die or 3-D packaging is becoming popular to reduce the footprint and total cost of a package and enable system-in-package (SiP) design through functions integration.

Several types of stacked die CSPs are available on the market. An example memory application is stacking of SRAM and flash die in a stacked die ball grid array (SDBGA) package, which can reduce the total footprint by 28 percent. Figure 1 shows several variations of stacked die interconnect structures for SDBGAs, including wirebond/wirebond, wirebond/flip chip and flip chip/wirebond.

Figure 1. Different interconnects for SDBGA.
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Traditionally, microelectromechanical system (MEMS) accelerometers have been packaged with a small outline (SO). A new package design for dual- and three-axis accelerometers, intended to reduce the package footprint, is targeted for consumer products as well as industrial automotive and telecommunication applications. Quad Flat No-Lead (QFN) is a type of lead frame CSP, commonly used as a low-cost solution for applications with low pin count requirements.

Product manufacturers are concerned with board-level solder joint reliability of stacked die CSPs during thermal cycling tests. To ensure reliable product functionality under extreme operating conditions, the typical thermal cycling test performance required is a minimum of 1,000 cycles under –40° to 125°C.

The process of thermal cycling tests, however, is costly and time consuming. Therefore, finite element modeling is widely used as an analysis tool for solder joint reliability — especially during the design stage of new packages, because of advances in high-speed computers and the development of sophisticated finite element models. There are many methods used by researchers to model fatigue life. Darveaux's methodology is a common approach, which involves both energy and damage accumulation theories. Life prediction accuracy of ± 2× generally is considered adequate, because of the complex nature of solder material's creep behavior and the uncertainty in board-level thermal cycling tests.

Figure 2. Schematic of flip chip/wirebond SDBGA.
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A detailed modeling analysis was performed for both SDBGA and SDQFN packages to study six common design parameters on solder joint fatigue life. Certain design guidelines often used in CSPs may not be applicable for stacked die CSPs. The behavior of critical solder joints in stacked die CSPs is more critical than in single die CSPs.

Solder Joint Fatigue Models

3-D models were constructed for stacked die CSPs to predict the fatigue life of solder joints during the thermal cycling test. Figure 2 shows a schematic diagram of a 0.5-mm ball pitch lead-free SDBGA, 88 I/O, with 3.6 × 3.5-mm die on top and 5.0 × 5.0-mm die on bottom, using mixed flip chip and a wirebond interconnect.

Figure 3. Schematic of SDQFN.
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Figure 3 shows a schematic diagram of SDQFN with 32 leads, eutectic solder and 0.65-mm lead pitch with ASIC die on top and a sensor die/cap on bottom, in a 7.0 × 7.0 × 1.8-mm package. The wafer cap protects the sensor die, and they are bonded together by glass frit before the package assembly. Protection of the fragile micromechanical structures is achieved by wafer-level packaging.

Table 1. Thermomechanical material properties.
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Temperature-dependent material properties were considered for materials used in both SDBGA and SDQFN packages. For lead-free (SnAgCu) and eutectic solder materials, Anand's viscoplastic model was applied to describe creep behavior. The rest of the materials were assumed to be linear elastic, and the board was considered orthotropic. Thermomechanical material properties are listed in Table 1.

Failure and Life Prediction

Darveaux's approach applies Anand's model of ANSYS to calculate the average strain energy density (SED) per cycle accumulated along the critical failure interface. The SED obtained from the viscoplastic modeling can then be related to compute the characteristic life:

η = a/[C1(SED)C2]

where h is the fatigue life at 63.2 percent failure rate, C1 and C2 are correlation constants and a is the length of critical interface (soldermask opening size or lead length). This modified approach does not take into consideration the crack initiation life and assumes that crack propagation life is dominant. This assumption is supported by good modeling/thermal cycling test correlation obtained for single die CSPs. The correlation constraints derived are extended for life prediction and design analysis of stacked die CSPs.

Figure 4. Position of solder balls and die edges.
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The critical solder ball of SDBGA was studied at (4,4) position, between 3.6 × 3.5-mm top die and 5.0 × 5.0 bottom die, and the potential failure interface was along the top solder pad layer with high SED (Figure 4). The localized die edge effect was more dominant than the distance to neutral point (DNP) effect for solder joint reliability. The most critical solder ball was not at the outermost corner. The characteristic life predicted for this model is 5,097 cycles with 1.6-mm board thickness, under –40° to 125°C (1 hr/cycle) thermal cycling. This design configuration of SDBGA is considered good, because the critical load is almost evenly distributed among the solder balls — instead of concentrating on one critical solder ball. Knowledge of critical solder joint position is useful when designing anchor balls or dummy joints.

As for SDQFN, the critical solder joint was under the corner peripheral leads, with potential failure along the top solder and lead interface. The characteristic life predicted was 1,560 cycles with 1.6-mm board thickness, under –40° to 125°C (1 hr/cycle) thermal cycling. For both SDBGA and SDQFN studied, the failure mode and location were close to their single die packages.

Design Analyses of Stacked Die CSPs

The SDBGA and SDQFN fatigue models were applied to study design variations of six common design parameters: thickness of die, package, substrate/lead frame and board, as well as solder joint standoff and solder pad opening size. For parametric studies, one design variable was changed at a time with respect to the control case, and then the percentage of difference was calculated.

Effect of Die Thickness. For both SDBGA and SDQFN, thicker stacked die helped to increase the life fatigue slightly. This trend is different than previous experience on single die BGAs and QFNs, which prefer thinner die. The same design guidelines learned from single die packages may not all be applicable to stacked die packages, because of the complex behavior of multiple die layers.

Effect of Package Thickness. For both SDBGA and SDQFN, a thinner package helps to enhance fatigue life. Therefore, a lower wirebonding loop height is desired for stacked die CSPs, to reduce the mold compound thickness. This can be achieved using reverse wirebonding. With increasing die stacking layers, a thin wafer (100 µm or below) is required, making backgrinding and handling critical as further stacking assembly steps.

Effect of Substrate/ Lead Frame Thickness. For SDBGAs, a thicker substrate improves the fatigue life by increasing the mean package coefficient of thermal expansion (CTE), and reduces global CTE mismatch with the board. As for SDQFNs, a thicker lead frame significantly improves solder joint reliability because the copper material (17.7 ppm/°C) has close CTE to the FR4 board (16 ppm/°C) — inducing less strain to the critical solder joint. Substrate and lead frame thickness are a design constraint, since they usually add additional cost to the package.

Effect of Board Thickness. PCB thickness is a critical design consideration, especially for end customers, because different board designs may be chosen for various applications. For both SDBGA and SDQFN, a thinner board is preferred because there is less global CTE mismatch between the package and board — resulting in longer fatigue life. This reliability requirement supports the technology trend of CSPs and portable devices.

Effect of Solder Joint Standoff. For both stacked die CSPs studied, higher solder joint standoff is preferred. This is a general design improvement for most BGA and QFN packages, and is applicable to single and stacked die packages. The larger separation distance of solder helps reduce the shear strain induced during thermal cycling. For SDBGA, because of constant solder volume, higher solder ball standoff results in smaller maximum solder ball diameter, which helps enhance fatigue life.

Effect of Solder Pad Opening Size. A larger soldermask opening size (for SDBGA) or longer lead length (for SDQFN) helps improve fatigue life. According to Equation 1, a larger pad opening size requires additional time for a crack to propagate through the failure interface (top solder pad) and will have a longer fatigue life. The solder standoff usually is lowered with a larger wetting pad area and results in a lower fatigue life. There is a need to compromise between the values of solder joint standoff and pad opening size.


Detailed solder joint fatigue models with life prediction capability were established for two types of stacked die CSPs. For enhanced solder joint reliability of stacked die CSPs, it is generally recommended to choose thicker die, a thinner package, a thicker substrate/lead frame, a thinner board, higher solder joint standoff and a bigger solder pad opening size.

Certain design rules learned from single die CSPs are not applicable to stacked die CSPs. The position of the critical solder ball is a variable for SDBGA, so the common practice of using dummy balls for the outermost corner position may not improve the fatigue life. Effects of design variables may be case dependent, so fatigue modeling is efficient to assess solder joint reliability of new package designs — providing cost, time and manpower savings to perform the actual thermal cycling tests.


For a list of references, please contact the author.

TONG YAN TEE, CAE team leader, may be contacted at STMicroelectronics, 629 Lorong 4/6 Toa Payoh, Singapore 319521; (65) 63507703; e-mail: tong-yan.tee