Intel: Challenges of Leadership
Have you ever been in a foot race? Some people think that the lead position is the place to be at all times, but I've often thought that the spot just behind the leader is best, then you can pace your progression and plan your break, holding on to your strength until the end. A leader must keep their eyes open and forward while sensing how close footfalls slap the surface behind them.
Recently Intel announced it has begun eliminating 95 percent of the lead used in its processors and chipsets. Last year the process began as the company shipped its first lead-free memory chips. The plan was to transition new packages as manufacturers were able to handle them in the complete board assembly and reflow process. Solder is used on leaded balls attaching the chip to the package, the package to the board. The research on which solder to use and how to adjust equipment to the new material took time. On the day that Intel made the announcement, National Semiconductor announced that it also had lead-free packages to offer as part of a global effort to protect the environment and provide a complete line of IC products by the end of this year. Footfalls.
Intel also announced that it has begun a $2B construction project to convert a 200-mm wafer fabrication facility to a state-of-the art 300-mm facility. We toured the new facility, the first Intel conversion of its type. It required a complete modification of the cleanroom facility to accommodate the much larger 300-mm production equipment. Five 300-mm fabs provide the equivalent of approximately 10 200-mm factories, and this will be Intel's fifth 300-mm facility, increasing capacity quite a bit, keeping them ahead of the pack. More footfalls.
Many of the technology challenges faced by Intel's Assembly Technology Development (ATD) engineers are challenges of performance and density. No single technology component can meet performance needs; therefore, when toured the Chandler, Ariz., campus we observed how closely the many collaborative R&D projects between Intel's chip designers as well as silicon and packaging researchers took place.
"Intel leads the industry in 90-nm, low-k inner layer dielectric, solder thermal interface material and high-k gate dielectric," says Martin Rausch, Intel's ATD research manager. Success has been positive in lead-free packaging and folded stacked chip scale packages due, in part, to the company's ability to make silicon, package and board tradeoffs. Rausch then talked about problems with power delivery, thermals, signaling and flip chip interconnect.
While touring Intel, we found a company fully equipped and excited about the race to create advanced packages. Footfalls keep it going.