Applying Moore's Law to Wafer Test


Gordon Moore's 1965 observation that the number of transistors per square inch of silicon was doubling every year has, with modest variations, continued to characterize growth in the semiconductor industry. This significant technical evolution known as Moore's Law is made possible by the investments by our design and wafer fab brethren who strive to reduce line geometries and improve performance.

Through improvements in EDA, photolithography and materials, we are able to place more circuitry on a smaller chip — increasing functionality and complexity of the silicon device. Ironically, the benefits of increased density and complexity provide the greatest challenges to subsequent semiconductor operations.

Typically, as device complexity increases, wafer test cost increases (Figure 1). This is largely due to the increase in complexity of the wafer test hardware and the probe card. Today's wafer probe technology is predominately driven by mechanical structures of needles, pins and springs — all of which are limited in their ability to realistically and economically address a reduction in feature size or an increase in functionality. An increase in chip I/O usually affects the number of probes required to satisfactorily test the chip on the wafer to ensure that it is acceptable.

Figure 1. Device complexity increases as wafer test costs increase.
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The cost of a conventional probe card is directly proportional to the number of probes on the card — more pins means greater material cost, and more material means more labor to assemble the pins in the layout. Placing smaller features closer together presents a dilemma in how to achieve desired contact between a mechanical item and a photolithographic structure that have geometric tolerances an order of magnitude apart. This is exacerbated by the migration away from perimeter I/O to fully populated array I/O. The probe card must be capable of routing power and signal lines over an array with minimal signal loss.

If wafer test is to keep pace with the evolving silicon complexity, a change must be adopted that exploits a similar design and manufacturing infrastructure. Taking a cue from the latest high-speed and flip chip packages, photolithographic thin film processes on substrates duplicate the circuit performance of the chips under test. When applying such thin film structures to wafer probing, it enables test floors to keep pace with our wafer fab brethren. We can now also increase functionality and performance while reducing geometries and cost as a function of complexity. When using photolithographic techniques, the cost of building one probe or 1,000 probes makes little difference. As in the semiconductor device model, the primary costs are in the mask set required to fab the product. If one were to build only one or two probe cards using photolithographic techniques, the cost of the mask set would have to be amortized accordingly and the solution may not be cost effective for the application. In volumes larger than just a few cards for a device family, however, the economics become compelling.

The adaptation of a device-type technology for wafer probing has benefits beyond scalability and increased functionality. It leverages the same EDA and simulation infrastructure that provides more accurate and predictable performance of test tooling. Resulting repeatability and reproducibility provide significant operational cost savings that are amplified by the investment in ATE capital. Using test structures that replicate the "in package" conditions of the final device allow test engineers to maintain exact correlation to final test results. This full functional test at the wafer level reduces the operational burden on final test.

Moore's Law is self-fulfilling because somebody somewhere is always going to build a better chip. But Moore's Law need not be limited to wafer production. We can keep pace in wafer test by using the same technologies as used by design, fab and advanced packaging. But for us to do so, we must commit to providing the appropriate development funding necessary to bring this technology forward into wafer test so that we may contribute to the reduction in device cost.

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MARK DIORIO, president, may be contacted at MTBSolutions Inc., 2540 N. 1st St., San Jose, CA 95131; e-mail: