The Value of IC/Package/System Co-design
Blending engineering knowledge across IC/OSAT/OEM companies
BY NOZAD KARIM, DOUGLAS J. MATHEWS, SIMON MCELREA AND AKITO YOSHIDA
For today's advanced IC design projects, there is a crucial need for IC, package and system designs to be initiated in parallel. Using recent packaging projects for real original equipment manufacturer (OEM) products as examples, here is proof that such a parallel co-design effort pays off with time-to-market, manufacturing productivity and cost-savings gains.
Until recently, conventional wisdom behind design flow for electronic systems was that the various engineering groups — silicon, IC package and printed circuit board designers — work in relative isolation, with the overall design proceeding sequentially. For today's advanced systems, however, it takes a parallel design effort to ensure that a targeted product hits its market window at the lowest possible manufacturing cost, and does so without incurring any unnecessary development costs.
A recent project, for example, involved co-design of a system-in-package (SiP) that helped pull the complexity out of a network motherboard — putting it into a packaging solution. This co-design project enabled the motherboard to be reduced from 18 to 12 layers, and resulted in a $200 manufacturing cost savings per board for the company.
Stacking Die or Packages?
The importance of early three-way design collaboration is well illustrated with today's need for stacking logic and memory die in 2.5G cell phone handsets, personal digital assistants (PDAs) and other applications, which are now being accomplished using stacked chip scale packages (S-CSP). While stacked-die applications are just beginning, and will likely increase from three and four to five or more active dies, there are limitations to stacked-die packaging that can be solved with stacked packages such as extremely thin chip scale packages. For some applications, particularly when stacking increasingly diverse combinations of logic and memory, stacked-die solutions may be limited by die procurement logistics (multiple die sources); the need for better control of die costs; or yield and quality concerns, including the need to work with "known good die" when low yield issues exist.
Dictating Silicon Changes
Package solutions can dictate changes in silicon design or process technology that enhance overall manufacturing costs. Consider how it was determined, after extensive analysis of packaging options with an IC manufacturer, that the best package solution for a high-speed digital application was a 7 × 7-mm silicon die put into a flip chip package. The calculated changes involved increasing the silicon chip size by 18 percent and die bump pitch from 150 to 185 µm to make room for vias on the substrate. The additional vias under the die reduced routing constraints and eliminated two routing layers on the substrate. The additional silicon area allowed the addition of a decoupling capacitor to reduce simultaneous switching noise and voltage ripple during high-speed digital switching.
These changes resulted in a lower overall manufacturing cost for the IC manufacturer, despite the increase in silicon real estate, with an end-use system performance better than originally conceived. The increase in silicon real estate enabled use of a less costly packaging substrate with a larger bump pitch that saved $20 in manufacturing cost per chip while keeping the package form factor unchanged.
Roadmapping Fab Capability
Conventional wisdom tells us that moving to a smaller package reduces costs. For example, in a how-to example involving a telecommunications chip set with four 180-nm silicon technology ICs, four capacitors and eight resistors, the packaging solutions were increasingly less costly 35 × 35-mm (no die stacking), 27 × 27-mm (two-die stacking), or 23 × 23-mm (three-die stacking) plastic ball grid arrays (PBGAs) with equivalent ball pitches and ball diameters. Analysis with an IDM showed that the 23 × 23-mm three-die stack package provided the smallest, lowest cost solution from a system's point of view. Stacking similar die reduced trace routing on the substrate, decreased signal delay and brought the number of substrate vias to a minimum — all improving power and ground planes. Analysis revealed, however, that performance would suffer because die stacking in the smallest package brought on thermal problems when the stacked die were not ideally placed relative to the package's central thermal ball matrix. Thermal constraints could have been resolved by switching to 110-nm silicon technology, but at the time the IDM did not have that capability. As a result, it chose the 27 × 27-mm packaging solution — leaving the smallest package as an eventual target when 110-nm capability would be in place.
RF Package Challenges
Perhaps the consummate convergence of package design issues comes with designing RF board-level circuits into SiPs. This is an increasingly popular solution where, for example, cost-effective RF SiPs are in demand for wireless local and personal area networks (WLAN/PAN) and Bluetooth applications. For a package's effect on system cost, a key driver is how to leverage high-volume manufacturing using or adapting to existing or standard package solutions. With RF circuits, the delicate balance is in achieving the required electrical performance and still managing high-volume yields through judicious selection from a well-conceived array of packaging options.
OEMs and IC manufacturers are finding that meeting manufacturing cost, package size and circuit performance with any RF SiP requires understanding a complex set of variables, including understanding trade-offs in substrate and assembly choices. Unlike a packaging choice driven by a clear-cut thermal management problem, at the RF level there are electrical design issues that include potential changes to the RF front end every time a filter, transmission line structure or component balun is implemented or moved.
A first analysis by an IC manufacturer often reveals that the cost of a RF SiP may be more than the cost of the associated individually packaged devices. For end-system consumer markets where cost-reducing pressures are immense, the justification for moving to an RF SiP must be looked at in terms of overall value added that the subassembly may provide. This includes: smaller size, more functionality, elimination of inventory and placement of passive components used in assembly, RF system development with a reduced staff, eliminating costly board tuning and providing a higher level of tested parts. This reduces the overall test cost per function.
Working with these challenges, a recent example analyzed combining five baseband and RF die and associated passive devices in an 802.11b WLAN modem. The OEM's initial goal was to achieve a 33 × 27-mm module. Co-design work, however, showed that the module would best fit in a 25 × 25-mm layout, and that there were various design options to study to help control costs (Table 1).
Table 1. This co-design generated comparison chart, from which the OEM made its production selection, shows packaging options for an 802.11b WLAN.
An ideal approach would have incorporated shielding within the overmold (which was still in development), eliminated dam and fill, and eliminated components by burying filters and baluns in the substrate - all saving substrate area (i.e., fitting into 17 × 20 mm), time to market was the driving factor in selecting the final design. The OEM chose to take a less risky approach, even though the cost in volume would be greater.
The production SiP was 25 × 25 mm and used a standard 4-layer laminate substrate. The module provided multicompartment shielding for both circuit-to-circuit isolation and regulatory protection. In today's market with cycle times being key, this was a good decision that still left a clearly identified path of cost reduction for future versions of the package. The overall result of the co-design effort was that from start to finish this WLAN was put into high-volume production and came to market four to five months sooner than normally expected for a product of this complexity.
In another RF co-design effort, an IDM put a PDA-destined Bluetooth module without an antenna into a 1.7-mm-thick, 10 × 14-mm, 77-pad land grid array (LGA). The goal of the project was to have working prototypes within three months. Silicon was in design and early fabrication, which added technical risk to developing a package solution. With the communications that co-design enabled, the engineers were able to deal with multiple die and module design changes as they occurred.
The final Bluetooth module package included a two-die chip set, a low-impedance balun and a 30-dB selectivity filter embedded in the package's two-core laminate substrate. By working with packaging engineers on the co-design of this product, the IDM was able to develop the module schematic, define the bill of materials, eliminate eight surface mounted components, reduce cost by $0.35/package, meet prototype dates and achieve production-ready status in six months. Significant in this design was the adoption of embedded passive components to avoid the cost of discrete filters and baluns that, at a 1.1-mm height, compromised the 0.85-mm height restriction of the mold cap.
Work with OEMs and IC manufacturers has shown that with RF SiPs, cost saving may not be dramatic at the SiP package level. Savings may result from some combination of eliminating or reducing product shielding needs (simple manufacturing, lower system cost, and yield improvements); simplification of the motherboard design (e.g., the ability to move from 6-layer HDI to 4-layer standard); manufacturing benefits that include reduced component count, inventory and logistics, and lower supplier support; and improved new product cycle times, among other issues and improvements. Thus, RF SiPs are only properly evaluated through a total product cost of ownership evaluation.
Driven by Cost, Size
The advantages of co-design are illustrated by an effort that addressed how to package an OEM's design for a second-generation of a popular home gaming platform. The OEM's objective was to produce a lower cost, smaller gaming box. The earlier version of the platform included the graphics processor, mounted cavity down in an enhanced ball grid array (EBGA), and the central processor unit (CPU) in a PBGA. The new box combined the graphics and CPU functions into one IC using 90-nm low-k 300-mm silicon technology. Other than the basic footprint requirement and the fact that this chip produced 8W of power, the OEM was flexible in how it wanted to proceed, but was already considering a recommended 42.5 × 42.5-mm EBGA solution that was similar in cost to the package used on the earlier generation box.
The co-design effort developed a list of package solutions that included thermally enhanced PBGAs (TEPBGAs) — advanced packages that feature beefed-up laminate substrates (thicker copper planes, more thermal vias, etc.), die-up wire bonding, and over-molding using standard compounds, all for a much lower cost than an equivalent EBGA solution. The second generation of this package (TEPBGA-2) includes an embedded heat spreader that is left exposed after molding. Analysis revealed that a 35 × 35-mm TEPBGA-2 was the right size, but it could not adequately handle the combined requirement dissipating 8W of power and providing a low-stress environment required by the low-k graphics-CPU die.
Figure 1. Thermal air flow prediction through a popular gaming flatform. Courtesy of Flowtherm.
At this point it was logical that the TEPBGA package was the right cost-advantage direction, but it needed to be redesigned for the specific needs of the OEM's gaming box. Extensive co-design testing included breaking down an earlier generation of the gaming box so that lab engineers could measure actual die temperatures and model how heat flowed through the system (Figure 1). With data in hand, engineers modeled enhanced TEPBGA designs for greater thermal performance and less stress around the die region; modeled variables including thermally enhanced mold compounds, thicker plated thermal vias, filling vias with conductive epoxy, completely or partially removing the solder mask under the die area to provide direct contact to metal, using thermally enhanced die attach compounds, using thinner mold caps and various combinations with and without heat spreaders. For each combination in this test matrix, the co-design team compared thermal performance vs. reliability risk vs. package cost vs. manufacturability. The engineers built out the few favorable combinations for further testing that led to a final solution for a TEPBGA-3 (Figure 2).
Figure 2. One-eight symmetry temperature distribution model of a thermally enhanced PBGA.
With the optimized TEPBGA-3 solution in hand, the relative thermal performances and cost comparisons showed that packaging the combined graphics-CPU chip with the proposed EBGA solution with a thermal performance (i.e., ØJA or thermal resistance from the die junction to ambient) of 12°C/W would cost 2.75× (compared to a PBGA solution with an unsatisfactory ØJA of 18°C/W) while the cost of using a TEPBGA-3 with a suitable ØJA of 13.5°C/W was only 1.25×. The conclusion was that for a 25 percent cost increase over a standard PBGA, the OEM would get almost the same thermal performance as an EBGA for approximately 40 percent of the price. This packaging solution justified the requirement that the OEM faced an expense of approximately $750,000 to change its production mask set to accommodate die-up packaging. If marketing projections for the second-generation gaming platform play out, this OEM will save on the order of several million dollars per month because they participated in co-design early in the system's development cycle.
NOAZAD KARIM, vice president of Engineering; DOUGLAS MATHEWS, senior director for RF Design and Applications; SIMON MCELREA, senior manager of SiP products; and AKITO YOSHIDA, senior product manager of 3-D Packaging, may be contacted at Amkor Technology, 1900 South Price Road, Chandler, AZ 85248-1604; (480) 821-5000.