In the news
Getting the Lead Out
SANTA CLARA, CALIF. — Beginning later this year, Intel Corp. plans to eliminate 95 percent of the lead used in its processors and chipsets. The move is part of efforts to make its product packaging more "environmentally friendly" and to comply with the EU's Restriction of Hazardous Substances (RoHS) and Waste Electrical and Electronic Equipment (WEEE) directives. Banned substances under these directives include: lead, mercury, cadmium, hexavalent chromium, polybrominated biphenyls and polybrominated diphenyl ethers.
Intel will start shipping lead-free technology with its microprocessors and chipsets in Q3 2004, and embedded IA microprocessors in Q2 2004. The company is working with the industry to find a reliable solution for the small amount of lead still necessary inside the processor packaging to connect the silicon core to the package.
Intel qualified its first lead-free plastic ball grid array for use with its flash memory in 2001, and shipped its first lead-free product in 2002. The lead/tin solder previously used for connecting this package to the motherboard was replaced with a tin/silver/copper alloy.
The company's new flip chip ball grid array package also uses a tin/silver/copper alloy to connect the chip package to the motherboard. However, until the industry can certify a replacement that meets performance and reliability requirements, about 0.2 grams of lead is still used inside the sealed package to attach the silicon core to the package.
In other news on the lead-free front, National Semiconductor (Santa Clara, Calif.) also plans to offer lead-free packages for its complete line of IC products by the end of the year.
Green Light for STATS/ChipPAC Merger
FREMONT, CALIF. — ST Assembly Test Services Ltd. (STATS) and ChipPAC Inc. have received early termination of the waiting period under the Hart-Scott-Rodino Antitrust Improvements Act of 1976 in connection with the pending merger between the two companies. STATS is a semiconductor test and advance packaging service provider, while ChipPAC is a providers of semiconductor assembly and test services.
On February 10, 2004, the two companies announced that they had entered into a definitive merger agreement in a stock-for-stock transaction to create one of the world's premier independent semiconductor assembly and test solutions companies.
Under the terms of the merger agreement, ChipPAC stockholders will receive 0.87 STATS American Depositary Shares for each share of ChipPAC common stock. Consummation of the merger is subject to certain conditions, including approval of the STATS and ChipPAC shareholders, receipt of a private letter ruling from U.S. tax authorities relating to the tax treatment of the merger for ChipPAC stockholders and other customary conditions.
For more details on the STATS/ChipPAC merger, read this month's Industry Voices by ChipPAC's Chairman and CEO Dennis McKenna.
SIA Confirms Chip Sales Are Up
SAN JOSE, CALIF. — Worldwide sales of semiconductors in February 2004 rose 30.8 percent, reports the Semiconductor Industry Association (SIA), compared to February 2003. While total sales of $15.58 billion reflect a modest 0.2 percent increase from January 2004, the SIA noted that February historically has been a relatively weak month for chip sales.
"The strong year-on-year growth of more than 30 percent reflects the steady improvement in business conditions, a trend which we expect will continue throughout 2004," says SIA President George Scalise. "The modest sequential growth in worldwide semiconductor sales reported for February is consistent with normal cyclical patterns. While growth was largely driven by a rebound in corporate information technology spending, the current growth cycle extends to all end markets and major product areas. We are encouraged by the recovery in demand in the wireline communications sector. Customers remain cautious about inventories, and February shipments actually trailed semiconductor consumption. As a result, we do not expect inventory corrections will be a drag on chip sales going forward."
The SIA noted that sales of programmable logic devices and standard cells grew in February by 4.3 percent, driven by a recovery in the wireline communications market. Microprocessor sales declined by 0.7 percent, reflecting historic patterns of subdued PC sales in the month. Sales in the U.S. and Japan declined slightly, while all other geographic regions recorded increases. The wireless communications sector and consumer electronics, which propelled the growth cycle with strong, double-digit increases through year-end were also flat to down in the month, but are expected to exhibit renewed momentum as the year progresses.
MEPTEC Presents 'Innovative Semiconductor Packaging Technology'
By John R. Lynch, Advanced Packaging Advisory Board Member
The MicroElectronics Packaging and Test Engineering Council (MEPTEC) held a luncheon presentation, "Innovative Semiconductor Packaging Technology Trends," on March 11. Topics of discussion included semiconductor cyclical trends, drivers of IC business, packaging trends, wafer testing and emerging technologies.
Kulicke & Soffa's Joel Camarda began with a review of the semiconductor cyclical trends from 1993 to 2004, and explained the capacity in place vs. anticipated capacity needs followed by excess capacity cycle. Along with the yearly drop in actual selling price (ASP) for ICs, the need for productivity is ever-present and a key ingredient in competitiveness. Based on cyclical analysis, 2004-2005 may again see excess capacity.
Currently, the drivers for IC business are cell phones, PCs and consumer electronics (DVDs in particular). Together, they account for 10, 14, and 30 percent, respectively. The current total IC market approximates $194 billion, while total electronic sales are in excess of $1 trillion.
Expected during 2004 and 2005, cell phones are going through continuous upgrades in features and functions. PCs are being upgraded as replacements are needed to maintain productivity and accommodate new memory, speed and software requirements. Consumer electronics (read as DVDs) are ever more popular. Communications are expected to be a larger factor in 2005 when infrastructure again builds out. Camarda then described the cascading effects of worldwide electronic system production to the semiconductor market and in turn the supply base (materials and equipment).
Unusual in the typical upward production growth trend were 2001 and 2002, both of which demonstrated downturns of 14 and 4 percent.
The next area covered was a review of packaging trends. The emphasis was on the ever-increasing complexity and, perhaps, divergence of fab capabilities (I/O) and assembly capabilities (I/O). Feature size minimizations, driven by materials, device design, lithography and interconnection architecture on the wafer side are moving at a faster rate than conventional assembly capabilities. Space transformation continues to be the challenge and, along with it, current densities, heat dissipation, equipment and processes. On the PC board level, the disparity is even greater in regard to density and transformation. Current IC assembly wire bonding best practice approximates 40-µm pitch.
Wafer testing is another challenge that must be met, not only for density, but for lead-times, test times and cost competitiveness. K&S is achieving increased density and decreased lead times by several probe card technologies and logistical approaches: modules that are 70 percent complete and ready for customization, vertical test technologies, area arrays, micro-springs and decreasing pad pitch capability.
The last topic of the talk centered on emerging technologies. Technologies singled out included: stacked die; thinned die/wafers; copper wire/bond interconnection; looping — reverse bonding; low-k dielectric; low-temperature bonding; stud bumping; multi-tier; new test socket development; and, advanced materials — bonding tools and wire.
The bottom line of the presentation was that new packaging technologies must continuously be developed and are required to remain competitive; to continue to bridge the gap between wafer technology and assembly/test technology; and to continue to achieve higher productivity and greater capabilities all at lower costs.
NEMI, IEEE's CPMT Society Work on Roadmap
HERNDON, VA. — The National Electronics Manufacturing Initiative (NEMI) and IEEE's Components, Packaging and Manufacturing Technology (CPMT) Society are working together to map the future manufacturing needs of the electronics industry to identify key technology and infrastructure developments required to ensure leadership of the global supply chain over the next 10 years. The goal is to help companies anticipate shifts in product requirements and to provide an early warning of changes in technology or infrastructure.
The duo are also working together on conferences, and are coordinating a NEMI tin whisker workshop as part of NEMI's Electronic Components and Technology Conference (ECTC), to be held June 1-4 in Las Vegas, Nevada.
Agilent Opens SOC Design Center in India
PALO ALTO, CALIF. — Agilent Technologies has established a System-on-a-chip (SOC) Design Center in Gurgaon, India, near New Delhi. The center, part of an existing facility that employs 1,000 Agilent workers, provides ASIC (application specific integrated circuit) and system design services to customers of Agilent's ASIC Products Division.
The Design Center addresses all aspects of ASIC development, including high-level design, logic design, physical design, verification and system firmware design. Agilent expects the SOC design center to be staffed with approximately 50 engineers by the end of 2004.