Logic and Memory Package Integration
Addressing technical and logistical challenges
BY CRAIG MITCHELL
Delivering enhanced features and functions in smaller electronic products has presented the electronics industry with a range of design and assembly challenges. Handset manufacturers, in particular, are driving toward lower-cost, smaller sizes, and reduced component count in products that offer improved functionality and an enhanced user experience.1 To develop these next-generation convergent products, designers are forced to weigh a broad range of trade-offs, including how to deliver desired features and functions without sacrificing size, cost, time-to-market or supply chain efficiencies.
The semiconductor industry has been exploring the package's third dimension to address many of the integration challenges associated with developing products that provide greater functionality in smaller form factors. Mobile phones represent the most significant application for 3-D packages today. Other applications include portable consumer products such as digital camcorders and cameras.2 Currently, the most widespread 3-D packages use die-stacking technologies within a single chip scale package (CSP). These die-stacked components are being broadly adopted for combining high-yielding memory devices, such as SRAM and flash, which have similar size and wiring requirements, low power dissipation and established wafer supply relationships.
Defining the Challenges
As handset manufacturers drive toward greater system-level integration, the industry is exploring the feasibility of stacking mixed device types, such as logic and memory, within a single package. While die stacking continues to be an effective solution for stacking similar device types, some key issues emerge with die-level integration of mixed device types (Figure 1).
Figure 1. Key challenges associated with die-stacking mixed devices.
Die Supplier Management. Placing chips from multiple silicon vendors into a single integrated package introduces several complex business and supply chain management problems.3 When an OEM design demands a package incorporating chips from multiple silicon vendors, these vendors must create business relationships allowing packaging of their chips with chips from other suppliers. To this day, these business relationships remain difficult to establish and manage. Accountability presents further potential difficulties. When several silicon vendors provide chips for a multichip package, it can be difficult to decide who is responsible for overall component quality. Is it one die supplier or the other? Is it the package assembler? Confidentiality is yet another concern. Many silicon vendors consider their final test vectors proprietary and confidential, and they are sometimes unwilling to make them available to the party responsible for the integrated product.
Test and Burn-in Management. Placing multiple chips into a single integrated package can create many problems. Some devices in the multichip solution may require full functional test and possibly burn-in after final package assembly, and it may not be desirable to submit one device in the stack to the mandatory burn-in conditions of another device. Furthermore, all silicon vendors with chips in the package need to provide their test vectors to ensure final product quality. To mitigate this problem, the packager must rely on the silicon suppliers' known good die (KGD) programs to ensure the ultimate quality and yield of their multichip component. KGD programs are somewhat common today, but there are costs associated with these programs due to tighter defect margins, longer test times on more expensive test equipment, and higher risk for potential compound yield losses at the module assembly level. In addition, KGD programs frequently do not apply to leading-edge IC processes or chip designs.
Table 1. This table shows the package stacking benefits for the silicon vendor and the system OEM.
Yield Management. Even with KGD and other testing methods, complete testing of die before packaging remains difficult with today's solutions. Yield is an important consideration with multichip packages, because costs can increase dramatically as a result of compounding yields as more chips are placed in a single package. The risk for implementing any high-value chip into these packages remains significant — if the lower-value chips are found damaged or defective following assembly into the chip stack, the higher-value chip must be discarded.
For these and a number of additional technical and logistical considerations, the industry is exploring new package-stacking technologies that provide the desired level of integration, while also addressing the challenges associated with die stacking mixed device types.
Packaging Stacking in Wireless Handsets
In a typical wireless handset, the base-band processor and memory components and interface bus require the highest level of I/O and wiring density. Providing a CSP platform to stack memory components on the processor not only saves space, but also allows for the integration of the memory bus in the stack, thereby reducing wiring density and cost in the motherboard itself. Trying to achieve this level of integration and density with die-stack technologies can be challenging in the substrate fabrication and assembly processes. But even when these technical challenges are overcome, the compound yield, test and logistics challenges often prevent die-stack technologies from being cost effective.
Figure 2. Packaging and testing devices before stacking provides testing and sourcing flexibility.
An emerging, stackable CSP* addresses this integration challenge by allowing different memory components to be stacked on a logic component, yet still use the current footprint, pin-out standards and existing industry infrastructure.4 Logic components can be produced, tested, marketed and sourced separately from the memory component — while still allowing a single CSP footprint (Figure 2). This approach also effectively addresses the assembly, business and logistics integration challenges many silicon suppliers face today with stacked-die technologies.
A more detailed discussion of this technology helps explain the mechanics and features of the 3-D packaging approach.
Figure 3. Stacked CSP optimized for stacking logic and memory chips.
The package starts with a two-metal layer substrate (Figure 4). The high I/O device is bonded to the two-metal substrate with either epoxy or silicone-based adhesive, and is followed by conventional wire bonding and overmolding processes. The substrate is then folded over and adhered to the mold cap, creating a memory footprint for surface mounting a pre-tested and burned-in memory component on top of the logic device. To test this package, slight modifications may be made to test the socket so that the fold tolerance does not affect contact registration.
Figure 4. Two-metal layer tape is available from several suppliers, including Compass, Hitachi Cable, Shindo and Ube.
Base logic and memory footprints can be designed to meet existing logic pin-out and footprint standards, allowing the DSP component to accept "off-the-shelf" memory devices — including stacked or combination memory components.
The package stacking process can be achieved at board-level in standard SMT lines to allow one pass through a reflow oven for all components, which results in little or minimal impact on standard board assembly processing.
The folding step is the only process that requires new equipment for a back-end CSP assembly line. The folding of flex circuit assemblies has been done for decades in the medical, military and consumer industries. An example is a flexible system integration module Sony has used to achieve the high level of integration and small form factor required for the latest generation of digital still cameras.
Figure 5. Package assembly process.
This sub-structure approach to stacking mixed device types is designed to address the die-stacking challenges described earlier. First, by providing a standardized memory interface between the baseband and memory components, handset manufacturers are able to source memory and logic devices separately from various, even competing vendors. Second, the fold-over flap makes it possible for the lower-yielding chip to be pre-packaged and tested prior to the attachment of the higher-yielding memory devices. Conversely, the memory devices can be tested and burned-in, if required, independent of the baseband chip. As only fully tested, pre-packaged devices are stacked, the package provides nearly 100 percent final package yield. The final stacking operation can be carried out by the semiconductor manufacturer after both packages have been assembled or by the board assembler just prior to or during board assembly. This technology provides a significant level of integration in a package nearly the size of the baseband chip itself.
Lastly, the technology is designed to scale to address higher wiring densities, smaller form factors, tighter interconnect pitches and higher levels of device and mixed technology integration. A high level of scalability is important when considering the rapidly evolving requirements of the wireless handset market.
The wireless electronics industry has been leading the charge for greater functionality in smaller form factors, demanding higher density memory subsystems (such as SRAM and flash) in the smallest amount of space possible.5 Die stacking will continue to be an effective solution for integrating similar device types, such as high-yielding memory chips.
As the industry drives toward mixed device integration, alternative approaches such as package stacking will be key to achieving higher levels of integration at an acceptable cost. Emerging packaging stacking approaches, such as the logic and memory technology discussed in this article, are designed to provide multi-vendor and die sourcing flexibility, while also driving down overall system cost by addressing the business and logistics issues associated with stacking mixed devices in a multichip package. The end result is more fully featured electronic products that meet the wireless industry's aggressive size, cost and time-to-market roadmaps.
*Tessera's µZ Fold-over technology.
CRAIG MITCHELL, vice president of marketing, may be contacted at Tessera Technologies Inc., 3099 Orchard Dr., San Jose, CA 95134; e-mail: firstname.lastname@example.org.