The Future of Package Design
Design collaboration is key
BY SANJEET UPPAL
Advancement of the electronics industry is dependent on three critical areas of hardware: PCBs, semiconductor packages and ICs. The ongoing drive for increased system performance at lower costs places the package physically and theoretically at the center of development. In systems, from cell phones to laptops to mainframes, the package must work to maximize the capabilities of the semiconductor's product technology. The package is required to cost-effectively meet three challenges: superior electrical performance, thermal performance and higher density.
Traditionally, semiconductor package development has followed closely behind advances in ICs (Figure 1). With advanced package technologies reaching a package-to-IC area ratio of 1:1, new issues such as routability arise. Market demands for highly complex products and fast time-to-market requirements require package design considerations to include the semiconductor, package and PCB as a single system.
Figure 1. This figure shows the fundamental evolution in packaging from basic DIP to high-density system-in-package (SIP).
As technology continues to advance at Moore's Law pace, the drive for lower cost and better economies is pushing integrated device manufacturers (IDMs) to rely on semiconductor test and assembly (SATS) providers for back-end assembly and test services. SIP designers have been forced to collaborate, because die placement in the package and assembly process flow greatly affect the success of the product. As technology advancement and outsourcing trends continue, four major forces — silicon and package integration, high-performance packaging, materials and test — will drive the need for increased semiconductor-package-PCB design collaboration.
Silicon and Package Integration
The package is no longer just an interconnect for the semiconductor, but rather an integral part of the system. Packaging technology affects electrical parameters such as operating frequency, power, noise, thermal characteristics and reliability. Perhaps more importantly, the packaging technology affects cost, which can determine success or failure of the product.
High data rate and high-frequency applications such as Gigabit Ethernet and 802.16 WiMax or the size/performance requirements for cell phones and mobile applications require the die, package and PCB to be considered as a system during the entire design phase. Ensuring a good signal path only within the outline of the package is no longer acceptable. Low voltages and high sensitivity to noise demand a complete system budget, rather than individual budgets for components. Short time-to-market requirements for many products force an overlapping design phase between the IC and package. An IC or package cannot be created in a vacuum, leaving the system/PCB designer to work around the performance requirements of the packaged IC. Perhaps a hidden advantage to codesign is the possibility to include components in the package such as baluns, antennae, filters, etc., where previously only basis RLC components were included. The added functionality provided by advanced components leads to a more integrated, solution-based product.
Assembly and test process advancement is quickly blurring the line between the start of back-end and wafer-level processing. Assembly and test processes carried out at the wafer level, such as bumping, offers lower-cost packaging solutions. Wafer-level processing also requires the integration of assembly between SATS and IDM, because the processing carried out by the IDM must be compatible with the SATS' process.
Through a collaborative effort, SATS can provide greater value add services. Package and test design, simulation and signal integrity capabilities available from SATS providers do not need to be duplicated by the IDM. Major EMS companies have been fully engaged in turn-key design and manufacturing for years. OEMS have realized the benefits of working with lower design overhead and, in many cases, lower product manufacturing cost, due to design for manufacturing (DFM) considerations. The advancement of original design manufacturers (ODMs) and EMS companies into the ODM model brings ODMs, IDMs and EMS to the same point for collaborating in package design.
Advances in semiconductor technology are challenging package technology to keep up. High-density I/Os with small pin spacing in high-frequency systems present a challenge to signal integrity, because of the possibility of increased noise, crosstalk and interference. Recent semiconductor technologies allow for lower voltages. While beneficial to power-sensitive mobile markets, lower voltage gates also intensify signal integrity issues. Improper terminations, reflections, ground bounce, etc. can all create enough noise voltage in reference to the operating voltage to cause signal distortion. In next-generation products, especially high-frequency applications, nearly every component of the package presents opportunities and hurdles to the proper operation of the product. In high-performance packages, careful consideration is required for impedance control and frequency characteristics, as a result of material properties and geometry. Manufacturing tolerances of package components, such as substrates, must be taken into consideration during design, because the combined tolerance stack can put a system out of its operational range. Modeling wire bonds, lead frames, pads, traces, vias, solder balls and power rings in relation to the IC and PCB, and designing for specific interconnect lengths, will ensure that the finished product meets the data sheet specifications.
Maximum heat dissipation has continued to increase in nearly every new generation of product. While the operating power in some products has decreased, the peak power and heat dissipation have greatly increased. As 90-nm technology becomes widely deployed, closer-spaced features on the die will result in further increased power density (Figure 2).
Figure 2. Heat dissipation for several generations of a CPU processor.
Increased heat dissipation is further complicated by uneven dissipation across the surface of the die. Many of today's new products use a clock gating technology that "turns off" blocks of the die that are not being used, or use multiple voltages on the same die by implementing on-chip regulators and distributed transistors. While this lowers power consumption, it creates non-uniform temperature across the die, which can cause reliability and performance issues. Gallium arsenide (GaAs)-based products are notorious for having "hot spots" that must be managed to ensure that proper temperature is maintained. To minimize the need for costly packaging or special end-product cooling requirements, it is critical for the packaging team to work closely with the IC designers to understand the end-product application concurrent to designing the package.
Materials present two areas for consideration. First, is the issue pertaining to the environment and special requirements for specific end markets. A number of new products are "disposable," with expectations that the product will be replaced every few years. The second issue is new, "exotic" materials. New materials are being used in all areas of the semiconductor, package and on the PCB-assembly side. The new combination of materials presents challenges to package integrity, contamination, material interaction and general manufacturability.
Environmental issues are fairly well understood, but continue to present challenges for packaging and products. Lead-free and "green" requirements force the replacement of many legacy materials in mold compounds, lead frames, solderballs, etc. These new materials do not have the same characteristics as the originals. By engaging early in the design process, packaging engineers provide input into package selection and bill of material (BOM) choices (Figure 3).
Figure 3. This thin array plastic package is designed for some of today's most demanding applications.
As semiconductor technology moves from 130 to 90 nm, 65 nm and, eventually 45 nm, new material sets are required in the foundry process. The recent introduction of low-k technology presents challenges from induced stresses that result in die cracking. In the future, high-performance ICs will likely change other materials, including dopants, which may affect package design and thermal budgets for assembly processing. Designers cannot create new ICs and hope to "throw them over the wall" for someone else to package. The introduction of revolutionary products using nanotechnology is further evidence of the need for an integrated approach to continue furthering technology in the market.
Collaboration among design teams is not limited to package design. Test and design for test (DFT) are also key areas for consideration. The International Technology Roadmap for Semiconductors (ITRS) has pointed to test as a top challenge to cost-effective manufacturing. Test, burn-in and yield can account for significant portions of the back-end processing cost and, therefore, drive final product costs. With higher data rates, increased device integration, embedded functionality, and with new semiconductor technologies, test begins to be a greater cost driver in terms of test time and required equipment. Additionally, test methodologies in use today, such as loop back, may become inadequate for high-performance and integrated products.
In many cases, IDMs reach the engineering build stage before giving consideration to test. Last-minute test development results in a less than optimum test plan and a delay in release of the product to market. Recently, industry-wide test capacity has tightened to the point where inadequate planning can cause significant issues with time to market and throughput — resulting in revenue loss. By working closely with the customer in DFT, a cost-effective strategy can be developed that takes into account logistics, test platforms and handlers.
SATS are striving to be virtual manufacturing locations for IDMs. To successfully meet their needs, SATS need strong customer application and design teams, and software packages to bridge the gaps between IC, package and PCB.
Technology advancement will continue in every aspect of the electronics industry. IDMs are continually driven to produce faster, smaller and less expensive products to meet the needs of new applications. The outsourcing trend is irreversible and, by market research predictions, will continue to grow in volume and services provided. Given blurring lines between OEMS, IDMs, EMS and SATS, cooperation is an inevitable requirement and an opportunity for shared success.
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SANJEET UPPAL, technology development manager, may be contacted at ASAT Inc., 6701 Koll Center Parkway, Suite 200, Pleasanton, CA 94566; (925) 398-0400; e-mail: firstname.lastname@example.org.