Issue



Bump Arrays for RF Applications: Step 5


05/01/2004







Modeling Methodology

BY N. IVAN NDIP, GRIT SOMMER, WERNER JOHN AND HERBERT REICHL

Area array packages are becoming compelling technologies for present and next-generation ICs. Most of the significant advantages offered by these packaging technologies over peripherally leaded packaging approaches arise primarily from the use of bump arrays for signal transmission from the chip to the package and the package to the board. However, as the operating frequencies of high-speed communication devices creep up the RF and microwave band, parasitics associated with bumps in these arrays may cause signal integrity (SI) problems that can limit the overall system performance. Thus, it is necessary to optimize the electrical design of these interconnects. Such designs require accurate electrical models for bump arrays that account for their parasitic effects in the GHz range. Most contributions made thus far are limited to RF and microwave characterization and optimization of a single bump or two-coupled bumps.1, 2

Geometrical and Material Parameters of a Bump Array


Figure 1. Bump array consisting of six bumps.
Click here to enlarge image

To illustrate the modeling methodology for bump arrays, flip chip interconnects (bumps) are used in Figure 1, showing a bump array that consists of six-coupled bumps and the relevant electrical parameters for its characterization. All bumps in the array are geometrically and materially identical. The conductivity of the bumps used in this example is approximately 6.7E+06 S/m, and the relative dielectric constant of the substrate is 3. Each bump has a height and diameter of approximately 2 mils. A constant pitch of 100 µm was maintained between bumps.

Modeling Methodology for Bump Arrays

Successful characterization of bump arrays using this methodology depends on the fact that electromagnetic (EM) coupling between any bump and its "next but one neighbor" and beyond can be neglected. This is the case in most RF and high-speed packages. Neglecting this coupling and considering the symmetrical arrangement of bumps in an array leads to a reduction in the number of electrical parameters to be extracted. Thus, in characterizing a bump array, only the following parameters are needed:

  • Resistance (R) and inductance (L) of a single bump;
  • Mutual inductance and coupling capacitance between any two parallel (Mp, Cp) and two diagonal (Md, Cd) bumps.

Once these parameters are extracted, EM interaction between multiple bumps must be examined. In view of this, we considered a triangular and a parallel arrangement of three-coupled bumps, and justified that:

  • Effects of EM coupling between diagonal bumps (for example, B4 and B6) on EM interaction between any two parallel ones (for example, B5 and B4, B5 and B2 or B4 and B1) can be neglected, and vice versa;
  • Effects of EM coupling between outwardly placed bumps (for example B4 and B6) on EM interaction between any two adjacent ones such as B5 and B6 or B5 and B4 can be neglected and vice versa.

Due to space limitations, only the justification in which the parallel arrangement of three-coupled bumps is considered will be presented in this article.

Extraction of Resistance and Inductance from a Single Bump

For the extraction of these parameters, parameterized equations for a single bump were used.3 For the development of these equations, a design of experiment (DOE) was set up and full-wave EM field simulations of 3-D models of a single-bumped flip chip were performed using software for 3-D electromagnetic analysis in a frequency range of 1 to 30 GHz.

Based on the field simulation results, a Pi-equivalent circuit model was developed and validated using RF and DC measurements of fabricated test structures. In this Pi-model, the bump is represented by a serial connection of resistance and inductance. The capacitors connected to the ground designate parasitic capacitances between the pads and the substrate/chip ground metallizations, respectively. Each element in this equivalent circuit model was then represented as a function of geometrical and material parameters of the flip chip interconnect.

Approximately 19pH was extracted as the bump's inductance, with 17 mΩ as an average value for its resistance. Since this work focuses on the modeling of bumps, results of investigations performed for the characterization and optimization of pads will not be presented.

Extraction of C and M from Two-coupled Bumps

In a bump array, EM coupling between two diagonal and parallel bumps must be examined separately. For both configurations, two separate two-port models — "short" and "open" — were used for the extraction of C and M, respectively. The reason is that the values of C and M obtained from a four-port configuration of two-coupled bumps are the same as those separately extracted from two-port "short" and "open" models of two-coupled bumps, respectively. This technique permits a validation of the extracted values using RF measurement results of test samples performed with a two-port vector network analyzer.

In the "short" arrangement, M is dominant because a metal plane places both bumps at ground potential. Since this hinders the existence of electric field lines between the bumps, the "short" model is not suitable for the extraction of C. Hence, the "open" model in which both bumps are separated was used for the extraction of C.

Values for L and R, obtained from a single bump, were used to characterize each bump in the equivalent circuit for two-coupled bumps. Through a linear circuit simulation, approximately 5.4 pH and 1.6 fF were obtained for Mp and Cp, respectively.

For the extraction of Cd and Md from two diagonal bumps, a triangular configuration of three-coupled bumps was used. For illustrative purposes, only the bumps and their coupling electrical parameters are shown in Figure 2.


Figure 2. Triangular arrangement of three-coupled bumps (shown on left), and their equivalent circuit model.
Click here to enlarge image

Based on the EM field simulation results, an equivalent circuit model (shown on the right side of Figure 2) was developed. In this circuit, Mp and Cp (represented as 2 × Cp/2) extracted from two parallel bumps were used to characterize EM coupling between bumps 1 and 2, and bumps 2 and 3. Circuit simulations were then performed, and 0.97fF was obtained for Cd. For the extraction of Md, all Cp/2s and Cg/2s were short-circuited. Approximately 2.9pH was then extracted for Md.

Illustrating Negligible Effects of Outward-placed Bumps

For both "short" and "open" configurations of three parallel bumps, EM field simulations were performed using 3-D EM models of three-coupled bumps. The equivalent circuit model, shown on the right side of Figure 2, was used for the circuit simulations. Values of R, L, Cp and Mp characterizing a single bump, and EM coupling between any two parallel bumps, respectively, were assigned to their respective components in the equivalent circuit model. C13 and M13, substituting Cd and Md in Figure 2 and designating EM coupling between outward-placed bumps, were each assigned a value of 0 (implying that this coupling is not considered). A comparison was then made between S-parameters extracted from:

  • The EM field simulation of three parallel bumps;
  • Circuit simulation in which C13 and M13 were extracted;
  • Circuit analysis in which Cp and Mp were used to characterize three parallel bumps while C13 and M13 were set to 0.


Figure 3. EM and equivalent circuit models of a bump array consisting of four-coupled bumps.
Click here to enlarge image

Results of this comparison showed that EM coupling between outward-placed bumps has little or no effect on the EM interaction between any two adjacent ones. Experiments carried out to investigate the reverse effect revealed that whether or not EM interaction between any two adjacent bumps is considered EM coupling between the outward-placed ones remains almost unaltered. This coupling was neglected in this work, because its values lie between -79 dB at 1 GHz and -44 dB at 31 GHz for the "open" arrangement, and between -65 dB at 1 GHz and -34 dB at 31 GHz for the "short" configuration.

Modeling Methodology

To validate the modeling methodology, field simulations using 3-D EM models of a bump array consisting of four-coupled bumps were performed (Figure 3). To each electrical component in the equivalent circuit model for a four-coupled bump flip chip, values of electrical parameters obtained from a single bump and two-coupled bump flip chip interconnects were assigned as follows:

  • L and R from a single bump were used to characterize each bump in the array;
  • Cp and Mp extracted from two parallel bumps were used to characterize EM coupling between any two parallel bumps in the array;
  • Cd and Md obtained from two diagonal bumps were used to characterize EM coupling between any two diagonal bumps in the array.


Figure 4. Characterizing a bump array using electrical parameters from single and two-coupled flip chip interconnects. Correlation between curves validates the modeling methodology.
Click here to enlarge image

A linear circuit analysis was then performed, and resulting S-parameters characterizing the bump array were extracted. A comparison was then made between these S-parameters and those obtained from EM field simulation of the bump array (Figure 4). As a result of the symmetrical arrangement of bumps in the array, S3.1 and S3.2 represent all other coupling coefficients between the bumps. The correlation between the curves shown in Figure 4 was also observed when the "open" arrangement was considered.

Conclusion

For typical bump pitches used in RF and high-speed packages, such as flip chip, electrical parameters extracted from a single bump and two-coupled bumps (parallel and diagonal) can be used to characterize any bump array.

References

  • Hussein, H.MG., El-Badaway, E., "An accurate Equivalent Circuit Model of Flip Chip and Via Interconnects," IEEE MTT-S Digest, Dec. 1996. Vol. 44, No. 12: pp. 2543-2553.
  • Jentzsch, A., Heinrich, W., "Optimization of Flip Chip Interconnects for Millimeter-wave Frequencies," IEEE MTT-S Digest, June 13-19, 1999. Vol. 2: pp.637-640.
  • Ndip, I., Sommer, G. et al., "RF Modeling of Single and Coupled Flip Chip Interconnects on HDI Substrates," IMAPS-14th European Microelectronic and Packaging Conference and Exhibition, Friedrichshafen, Germany, June 23-25, 2003: pp. 190-195.

Editor's Note: This article was originally presented at IMAPS' 36th International Symposium on Microelectronics in Boston, MA, Nov. 16-20, 2003.

N. IVAN NDIP, research engineer, et al. may be contacted at Fraunhofer Institute for Reliability and Microintegration (FhG-IZM), Gustav-Meyer-Allee 25, D-13355, Berlin, Germany; 49 (0) 30 46403 141; e-mail: ndip@izm.fraunhofer.de. GRIT SOMMER leads the RF Modeling and Simulation Group at FhG-IZM; WERNER JOHN heads the Advanced System Engineering department at FhG-IZM; and HERBERT REICHL is the director of FhG-IZM and the Research Center for Microperipheric Technologies at the Technical University of Berlin.