Trends in Wafer-level Packaging of MEMS
MEMS PACKAGING SOLUTIONS
Figure 1. Functionalities of packaging ICs (top) vs. MEMS (bottom).
BY K. BAERT, P. DE MOOR, H. TILMANS, J. JOHN, A. WITVROUW, C. VAN HOOF AND E. BEYNE
Microelectromechanical systems (MEMS) are miniaturized systems with electrical and non-electrical components. They will be indispensable parts of the intelligent devices of the future, because they can add new functionalities or supply energy. But compared to IC development, interactions are more complex between technology, component and application in these systems. Therefore, concurrent engineering that addresses modeling, simulation, technology, packaging and reliability in parallel is essential.
The packaging of MEMS is a determining factor in their functional behavior, as well as their production cost. A MEMS package typically has to fulfill the requirements of an IC package and provide additional functionalities that are specific to its application. To provide cost-effective solutions, the MEMS community is facing the challenge of developing packaging methods that can be applied to a wide range of devices.
MEMS vs. IC Packaging
The goal of IC packaging is to provide physical support and an electrical interface to the chip and to isolate it physically from its environment. MEMS devices, on the other hand, often are interfaced intimately with their environment and are less generic in nature. Consequently, MEMS packaging must address different and more diverse needs than IC packaging:
- MEMS do not obey scaling laws like ICs do.
- MEMS consist of a larger variety of basic building blocks; sensors and actuators can be comprised of acoustic, chemical, magnetic, optical, pyroelectric, resistive and thermoelectric elements.
- MEMS' packaging functionalities are inherently broader. IC packages must accommodate ever-denser electrical I/Os and increasing levels of electrical power and thermal dissipation. Ambient parameters such as moisture or pressure are treated as undesirable noise signals to be isolated from the IC by the package. In MEMS packaging, the electrical I/O typically is unidirectional and less dense. The electrical and thermal power handling is less demanding, but at least one of the non-electrical influences becomes a desired input.
Due to additional packaging requirements for MEMS, the classification of traditional IC packaging into at least four hierarchical levels of packaging is less applicable to MEMS. While wafer-level packaging (also known as 0-level packaging) for ICs comprises the interconnection of numerous transistors, gates or cells within the chip itself, wafer-level packaging of MEMS encompasses all wafer-level operations. 1-level packaging is performed after individual MEMS devices have been extracted from the wafer.
Trends in MEMS Packaging
MEMS processes will likely never reach the high degree of standardization CMOS have achieved. Roadmaps for MEMS wafer processing and packaging are less mature and less useful than their IC counterparts. Still, four major trends in MEMS packaging and subsystem integration can be noted, based on the two main drivers of current MEMS development — cost reduction and miniaturization. These include:
- Compact hybrid IC-MEMS integration and packaging concepts;
- Increased use of thin-film, wafer-level packaging and system integration concepts;
- Growing synergies between MEMS manufacturing equipment and IC/MEMS packaging equipment;
- Trend toward low-temperature technologies that can be applied on a variety of substrates, such as IC wafers, glass and laminate.
Zero-level Packaging Concepts
MEMS in wafer form typically are extremely sensitive to their environment until they are packaged. They often contain fragile parts that can be damaged during back-end operations such as dicing, pick-and-place, wire bonding and soldering during exposure to particles. Protection in the early stage of the package is required. Therefore, 0-level (and/or 1-level) packages often contain a 'capping' function of the MEMS. This cap also can act as a structural part for MEMS devices that require operation in a vacuum, at reduced pressure or in an inert ambient. For devices such as micro-relays or micro-accelerometers, the ambient of the cavity housing of the MEMS device can play an important role in tuning the operating characteristics. The impact of the cavity realization process on the device performance must be kept to a minimum. This often necessatates low-temperature processing and the absence of any aggressive or corrosive agents during sealing. The cost of manufacturing must be reduced as much as possible, because packaging is a determining factor for the production cost of MEMS.
Figure 2. Capping of MEMS device as part of the packaging sequence.
Three approaches for realizing the encapsulation currently are in use: wafer-to-wafer bonding, die-to-wafer bonding and surface micromachining.
The general idea of wafer-to-wafer bonding is to cap the wafer containing the MEMS structures with a separate, micromachined wafer in which a small cavity is made or a stand-off ring is implemented. As such, a stack of wafers can be built. For the bonding of the wafer, several methods exist. The most prevalent techniques are anodic, fusion or glass-frit sealing. The process and materials used determine the hermeticity and controllability of the cavity ambient. This approach is well established, and dedicated equipment with high throughput and yield is commercially available. The main disadvantages of the method are the additional processing required for bond pad access, the limited topography that can be allowed for feed-through signal lines, and (especially in the case of fusion bonding) high process temperatures. However, recent developments using polymeric sealing materials and wafer-thinning techniques look promising in overcoming these barriers.
Die-to-wafer bonding offers a competitive alternative. Preprocessed and diced caps are being placed one by one on each MEMS device on the wafer by means of flip chip bonder. In the case of larger dies, the approach offers economical advantages over wafer-to-wafer bonding. For larger dies, the longer bonding process time for the mounting of individual caps is balanced by the fact that bond pads are readily accessible. The technique can be used for low-temperature sealing materials, including solder seals with hermeticity below 10-11 mbar l/s. It can also be used for thin caps.
Figure 3. MEMS wafer with wafer-to-wafer caps. After bonding, the cap wafer with preprocessed cavities is separated by wafer thinning.
A technique known as Indent Reflow Sealing was developed that controls inner ambient, based on wafer bonding in which chips are assembled by flip chip using a solder bond. An optional spacer layer is used underneath the solder layer to allow better control of the cavity height. Key steps of the technique are the creation of an indent and the closing of the indent during the solder reflow step in a designated oven. The method provides both hermeticity of the cavity seal and controllability of the cavity ambient, both essential features for packaging MEMS. The technique also has potential application for MEMS device packaging, in which a great flexibility with respect to the cavity pressure and ambient is required. Other features of the method are the use of low bonding temperatures (220°-350°C) and the ability to seal large batches of chip-on-wafer simultaneously.
The most compact method of hermetic sealing is to use thin-film caps made by micromachining. In this approach, the cavity contains an access channel for the sacrificial layer etchant. After completing the sacrificial layer etch, the channel is closed and the cavity is sealed. Closing the channel is done using reactive sealing techniques such as growing a conformal LPCVD layer or simply covering the hole. As compared to the other approaches, the horizontal dimensions of the cap can be shrunk to the area of the MEMS device underneath, and the cap thickness can be reduced to less than 50 µm. This technique is complex, but a noticeable advantage relates to the ability to seal a number of wafers simultaneously. The choice of cap material and sacrificial layer is to some extent specific to the MEMS device underneath, implying relatively high non-recurring development costs. In mass production of MEMS devices, the increased development effort can be offset by lowered production costs caused by the extended use of wafer-scale processing and savings in MEMS real estate.
MEMS packaging is not limited to the packaging of individual MEMS devices. It also encompasses the integration of MEMS into systems. This subsystem integration can be realized by conventional wire-bonding and mounting into standard packages, but increasingly compact packaging methods such as chip stacking and integration multichip modules are being developed for complex MEMS demands. Chip stacking is used to interconnect high-density imagers, displays or inkjets with thousands of pixels to their addressing and read-out ASICs.
Figure 4. A membrane of poly-Si(Ge) is surface-micromachined over the MEMS device and then hermetically sealed.
RF-MEMS devices, such as switches and resonators, are being integrated with passive RF components in a multilayer thin-film technology (MCM-D) module, resulting in true RF systems-in-a-package. MCM-Ds are formed by the deposition of thin-film metals and dielectrics, either polymers or inorganic dielectrics, on dimensionally stable bases such as silicon, glass or ceramic. The technology enables integration of passive components into the substrate or assembled in discrete form on the substrate. The adaptation of the RF-MEMS technology toward a MCM-D platform allows an optimization of the performance of RF switches and varicaps.
Cost and miniaturization requirements are driving the technology toward wafer-level processed packaging methods that can be applied to a wide range of MEMS devices. Subsystem integration of MEMS devices makes increasing use of advanced, compact packaging techniques such chip stacking and integration in multichip modules.
For a complete list of references, please contact the authors.
K. BAERT et al. may be contacted at IMEC, Kapeldreef 75, B-3001, Leuven, Belgium; + 32 16 281 266; e-mail: firstname.lastname@example.org.