MCP for Memory Components
BY DAN INBAR
As 2.5G and 3G smartphones shrink in size, yet offer increased functionality and a PC-like graphical user interface (GUI), original equipment manufacturers (OEMS) are reducing the number and size of onboard components. Memory manufacturers must now provide higher capacity memory in less space.
Multichip packaging (MCP) manufacturers met this challenge by combining multiple die or already-packaged chips in a single outer package. But they are being confronted by new MCP-related challenges of yield, performance, reliability and multiple sources.
Memory chips make up 45 percent of the total die area in today's handsets, comprising the third most expensive component. As the amount and type of data and code that smartphones store rises, reducing the percentage that memory chips occupies poses an ever-growing challenge.
Advanced packaging technologies such as MCP are effective in saving space. The total die area for the eight to 14 components on a handset has declined since 2000 from 18.9 to 8.6 cm. The possible array of memory components, diversity of manufacturers, and associated signal integrity and yield problems make the solution complicated.
In simple voice phones, two onboard memory components support voice operations and store personal data. Nonvolatile NOR flash is used to store code and user data, and a small random access memory (RAM) stores temporary information and variables.
NOR flash is less dense than NAND. As a result, the price of using NOR flash in multimedia handsets requiring high memory capacity is both cost and precious onboard real-estate. Even with MCP, using NOR requires more layers with more separators — making yield, package height and total area problems more acute.
Reducing Cost and Size with NAND-based Systems
NAND flash is being used in smartphones that require higher capacities to store more personal data, multimedia applications, and code to run applications and PC-like operating systems. But raw NAND flash is beset by limitations. Since its hardware interface is not standard, it requires an external chip to interface to the outside world. Unlike NOR flash, it does not support eXecute in place (XIP) functionality, preventing it from performing boot operations or any code execution.
As a result, using NAND in an MCP design increases the memory chip count (though reducing the cost) to four components: NOR flash for boot and code execution; PSRAM/SDRAM for shadowing and/or to store temporary information; up to 64 MB (512 Mb) NAND flash for data-rich applications; and an external interface chip (a controller) to enable the system to work with NAND's unique interface. The onboard surface of components mounted side-by-side in a smartphone is far greater than stacked inside an MCP. The MCP footprint is set by the single, largest footprint of all the chips packed inside.
Extending functionality in a single chip can reduce the total number of chips required inside an MCP. This approach carries with it at least a fourfold payload: higher yields, lower height, less interchip routing and performance testing.
NAND-based functionality can be extended to include resident, flash file management with an on-chip controller in a single die, eliminating the need for an external interface chip. It can also offer on-chip XIP boot capabilities to replace a separate boot device. Fewer chips are possible, but with the flexibility of adding other memory chips to meet varied design requirements. If all components are from the same manufacturer, testing-related difficulties are minimized.
Another method to maintain high reliability and yield, while enabling "best of breed" chips from different manufacturers to be used in the same MCP, is to implement known good dies (KGDs). KGDs are bare dies that have been tested to meet quality (such as guaranteed number of read/write cycles), data reliability and performance specifications before assembly into the final package. KGD levels vary and standards are not well defined, so manufacturers must conduct their own cost analyses to determine which level is most cost-effective for a particular MCP.
The most effective way to meet the MCP challenge will be increasing the functionality of individual components to reduce the chip count and MCP height, and to implement KGDs to maximize yield benefits.
DAN INBAR, associate vice president, may be contacted at M-Systems, 7 Atir Yeda St., Kfar-Saba, 4425, Israel; +972-9-764-5000; e-mail: firstname.lastname@example.org.