An Industry Perspective
BY ELLERY BUCHANAN
Even though flip chip technology has been in existence for the past 30 years, the ramp in production began during the last few years. Advances in substrate technology and material development have accelerated the adoption of advanced packaging technology. End-user applications requiring more complex and functional forms of device packaging continue to increase at a rapid pace. Along with this increase has come the need for more complex and functional forms of device packaging. Foremost among these growing advanced packaging techniques is the use of wafer bumping and wafer-level chip scale packaging (WLCSP).
Gold bumping, the most mature bumping market, is used primarily for packaging liquid crystal displays (LCDs). Most companies prefer buying cost-effective equipment for producing LCDs that is extendable to address future technology generations. Gold bump foundries are located primarily in Asia, with Samsung as the only exception, producing gold bumps for their self-manufactured LCD drivers.
Fine-pitch electroplated solder bump technology is used for bumping high-end devices, such as microprocessors, and high-performance logic such as digital signal processor (DSP) and graphics processors. This operation is dominated by large integrated device manufacturers (IDMs) and is an unlikely candidate for outsourcing. However, foundries in Taiwan perform the bumping operation for fabless companies. Screen-printed solder bump operation has also gained acceptance for cost-sensitive devices.
The WLCSP has emerged as a recent technology in which the chip is fabricated on wafer level, prior to singulation. Such devices have a typical ball grid array pitch and bump size that can be placed directly onto organic substrates with standard surface mount pick-and-place equipment. This technology may gain increased acceptance once it becomes cost competitive. Today, WLCSP has been adopted for mass consumer products where form factor is critical (digital cameras, watches and mobile phones). Passives and discrete components are using this technology. For such components, the cost per package is extremely low because thousands of individual chips are manufactured on one 200-mm wafer. WLCSP may also gain acceptance for high-speed memory, such as double data rate (DDR II). All major memory makers are currently developing this packaging capability. Once adopted by memory manufacturers, it will help establish an infrastructure for acceleration of advanced packaging. As the infrastructure matures, advanced packaging costs will decrease — making these technologies more suited for mid-I/O applications.
Wafer Bumping (Electroplating) Process
The six significant process steps involved in wafer bumping are shown in Figure 1.
Figure 1. These six process steps are significant in wafer bumping.
Wafer Preparation. This step is required to remove both organic and other residue prior to under bump metal (UBM) deposition. The cleaning also serves to roughen the surface of the wafer passivation and bond pad and promote better adhesion of the UBM.
Under Bump Metallization. UBM layers, after an etch step, are deposited by sputtering. The UBM should be able to provide excellent adhesion to a variety of wafer passivation and final metals (bond pads); hermetic sealing of final metals; low ohmic contact to the final metals; a final metal layer that ensures good wettability for a variety of solder alloys; provide sufficient wettable material to form intermetallic compounds with respective solder metals; and minimal processing stress to the wafer.
Coat and Develop. The photoresist is spin-coated on the wafer and distributed evenly on the wafer surface. A typical wafer bumping process flow involves two coating process steps. The first photoresist is applied to prevent the UBM layer from being etched. The second photoresist coat is applied to create the opening for solder deposition. A thick resist coating is required for the second resist layer, which requires different techniques in comparison to the front-end resist deposition. The develop after the exposure and the photoresist strip after the plating step may be conducted using spin-on tools or immersion tools, depending on fab logistics.
Photolithography. The layer of deposited photoresist is then patterned and developed. During the first level of patterning, the UBM is etched except in the areas over the bond passivation openings, test structures and alignment marks. The resist is removed, leaving the UBM over the bond pads. Patterning of the second photoresist layer creates the opening for the solder deposition. Thick resist lithography considerations are different as compared to front-end lithography requirements. High wafer plane irradiance is necessary to expose the thick resists used in advanced packaging. Lithography equipment should have a low numerical aperture that ensures the large focus range required, while processing thick resists. One of the most important factors in selection of any lithography tool is the ability to print defect-free images on a wafer, thereby eliminating the lithography tool as a yield detractor. Once a wafer reaches the wafer bumping process step, it is worth thousands of dollars. Any incremental yield loss during the photolithography process sequence results in a significant financial impact.
Device manufacturers are now using traditional front-end lithography equipment, such as steppers, to leading-edge back-end packaging applications because imaging requirements of wafer bumping are subject to the same production necessities as front-end semiconductor fabrication.
Metal Deposition and Metal Etch. Proprietary metals are electrolytically deposited on the UBM. Single metals, as well as binary and tertiary metal stacks, can be used, depending on the application. The material is deposited as column type (without reflow) or mushroom type (with reflow to form a ball-shaped bump). The resist and exposed UBM are etched away (before reflow) to reveal the bumps.
Figure 2. Defects such as bridged bumps are cause for concern.
Inspection. The deposited solder bumps are inspected to reveal any product defects. Defect detection consists of uncovering anomalies on the wafer pattern and measuring feature dimensions. Not all anomalies are defects and a powerful state-of-the-art system should be able to distinguish between defects and acceptable process variations. Defects of concern include: over/incomplete etch; lifting metal; mask/photoresist defects; residue; scratches; passivation holes; and bridged metal (Figure 2). Once anomalies are detected, data-refining software automatically clusters point anomalies into larger single defect types. User-definable criteria based on the size of the defect and location on the dies is used for further data refining. Another important aspect of refining the data is automated defect classification, which is used to specify the type of defect and provides powerful insight into previous process steps. In an inspection strategy in which inspection is a mere gate, specific criteria should be used to determine failure. Bad die may be inked or electronically tagged in wafer maps. In a more sophisticated operation, data are analyzed to provide feedback.
Flip chip technology is experiencing explosive growth. With the rapid increase in the adoption of advanced packaging techniques, there is a need for process development and equipment compatibility for seamless process flow. The developing infrastructure is key to widespread adoption of advanced packaging technology.
ELLERY BUCHANAN, chairman of the Advanced Packaging and Interconnect Alliance, may be contacted at Ultratech, 2907 Navidad Cove, Austin, TX 78735; (512) 347-0627; e-mail: email@example.com.