System-in-package: Strategy for Engagement
BY NEIL MCLELLAN
System-in-package (SiP) has long been "next year's technology" when considering the introduction of new packaging concepts. While OEMs and original design manufacturers (ODM) expect plug-and-play solutions, the design cycle for traditional system-on-chip (SOC) often runs to 18 months for advanced designs. Coupled with high design and mask costs, the SOC is kept out of the running for many system and subsystem functions. SOC solutions have longer cycle times and are much less forgiving to die revisions and minor functionality changes. With embedded memory and multiple format functionality integration, SOC is proving to be a nightmare for test — particularly for at speed testing required to isolate defect types common on 0.13 and 0.09 µm wafer designs. Compared to the SOC model, SiP advantages are clear from cost and cycle time perspectives, with a cycle time less than half that of the SOC.
SiP offers a key technical advantage, primarily by concentrating the radio frequency (RF) content of a circuit into a manageable module format. Traditional OEM models in which the circuit design is constructed of discretely packaged ICs that are paired with other ICs and passive components on the system motherboard are becoming increasingly complicated. SiP simplifies this complexity with its nature of plug-and-play performance. SiP solutions often include support software and design interface rules to simplify the end result of the final product.
It is said that one of the most valuable commodities in today's market is a skilled RF circuit designer able to handle complex system design needs. With the shortage of specialized design capability, system designers are often forced to bypass internal RF design layouts and integrate a SiP module design. This strategy decreases the cycle time of new product introduction by decreasing the system motherboard design content and eliminating design verification and optimization stages.
Optimization procedures are critical to the success in RF circuit design because the optimal tuning of the RF circuit depends on the actual signal impedance on any given section of the circuit. The signal impedance fluctuates according to the manufacturing tolerances of the IC, interconnect wires, traces on the substrate, passive component solder joints and variability in nominal values of the passive components (Table 1). These tolerances combine and result in interdependence, such that a given circuit that works well in a simulation program may not work well in reality. Given the tolerances observed, there is a certain yield loss to be expected, and SiP proves cost effective by isolating yield issues.
Building a SiP
Traditional SiPs consist of one or more IC dies mounted to a multilayer substrate combined with one or more passive components. The substrate can be either organic or ceramic, interconnect can be either wire bond or flip chip, and passives either soldered or attached by conductive epoxy. Each of the preceding choices affects the quality, performance and cost of the resulting SiP product. The choice of which path to take is driven by cost limitations and performance requirements of the given market.
One option is the single-layer metal (SLM) SiP, based on chemically milled packaging (CMP) concepts (Figure 1). Ceramic SiPs are expensive in regard to tooling and fabrication. Organic substrate ball grid arrays (BGAs) are thermally limiting, and integrated passives in multilayer SiPs are costly. For these reasons, SiPs have been known to challenge the patience of test engineers.
SLM SiPs are cost-effective and conduct heat well. They also provide quick access to multiple test access points or circuit nodes on the outside of the package, as well as offering certain passive structures at a low cost. SLM SiPs are available in low-profile formats, down to a total package thickness of 0.4 mm.
After choosing a SiP package format, the next step is to design the circuit layout. This is challenging, given that many SiPs are RF circuits and there is a certain "black magic" in getting the design right. During the design cycle, it is imperative that effective use of signal integrity tools is made. Again, though, this is the traditional process flow from concept to manufacturing. In some cases, there are other options to speed the design cycle and make the finished product more efficient. The trick is to integrate partial subsystem characterization (PSC) into the design flow.
Figure 2. High-frequency test apparatus.
Figure 3. Inductor library test structure.
After the rough design and netlist is complete, the SiP substrate is fabricated and passive components are placed. As previously mentioned, the signal characterization of the partially built SiP module depends on many variables and can depart substantially from what even the best computer-based model will predict. Use of a PSC design flow allows designers to measure the actual integrity of a given signal path through the SiP circuit, and to do so at the actual intended operating frequency. This is even more of a critical design step with SiP packaging because of the observed resonance and interaction of the SiP substrate with the passive components, and even wires from the die. The end result of the PSC exercise is that the final design proceeds faster from concept to finished product, and the passive values selected are made more accurately. This process provides a higher performance SiP.
While this simulation process sounds simple in practice, it requires an investment in manpower and equipment. Actual sample measurement at high frequency requires an S-parameter vector network analyzer, and to get the signal to the analyzer requires a high-frequency compatible Pico-probe (Figure 2). Analyzing the data requires software to convert the S-parameters to parasitic values and Q-factors.
Test Structure Design
As an example of how this might work in practice, we look at a test structure design library created by one company* for its offering in the SLM SiP package family (Figure 3). One feature of this type of SiP is that it can integrate easily onboard passive structures, in this case inductor coils. To characterize the effectiveness and repeatability of these coils, a test structure with various types of coils is constructed.
The inductance and Q-factor of the single coil path is then measured using a vector network analyzer over a given range of frequencies. Note the sharp dependence on frequency and also the observed resonance of the circuit (Figure 4). One observation made during the characterization of this test structure was a small deviation of inductance from sample to sample, with a standard deviation of less than 3 percent compared to an observed variance of 10 percent from commercial multilayer inductors.
After the SiP has been optimally designed using computer model signal integrity, RF technology and partial subsystem characterization, it is ready for assembly and test. Again, there are challenges that must be considered to make the best SiP possible.
SiPs are a combination of SMT and traditional package assembly. A critical consideration is the quality of the SMT and the post-cleaning of flux residues to ensure good adhesion of the mold compound to the SiP components and the expected moisture sensitivity level (MSL) rating. MSL-3 or better must be targeted, and a combination of solution cleaning and plasma techniques may be the best way to ensure high quality and reliability levels for SiP assembly. One variable is the increasing use of conductive epoxy (Table 2). While the interconnect resistance of the epoxy technique is higher than solder interconnect, the manufacturing flow is often more simple and the SiP performance is not significantly degraded.
Test follows assembly, a key part of the process. Considerations for test need to be made at the beginning of the design flow and, in many cases access to test nodes must be made to the outside of the package. In the case of fine-pitch BGA SiPs, this means that some of the external solder balls may not require soldering to the motherboard, but are there only for test purposes. In the case of the SLM SiP, access to most of the potential test nodes is straightforward because of the exposure to the outside of the package of all the interconnect metallization.
Table 1. The data shown in this table refers to overall resistance of copper pad, epoxy/solder, zero resistance components, etc. Further, the accuracy of measurement is ~0.02 Ω.
There are many choices and opportunities in today's SiPs. For integrated device manufacturer (IDM) designers, the first set of choices is SOC or SiP. Once the decision to go with SiP has been determined, there are a host of subsequent decisions to be made: the type of SiP solutions, how to plan for test, how to optimize the design to maximize yield and how to select the best assembly partner to offer the maximum support throughout the process.
Figure 4. The full frequency spectrum for an embedded inductor vs. a multilayer chip.
Table 2. The inductance and Q-factor of the single coil path, measured using a vector network analyzer over a given range of frequencies
NEIL MCLELLAN, chief technology officer, may be contacted at ASAT Inc., 6701 Koll Center Parkway, Suite 200, Pleasanton, CA 94566; (925) 398-0443; e-mail: firstname.lastname@example.org.