Package Selection for Design
BY GREGORY PHIPPS
As the industry continues to shrink die sizes and package footprint requirements, increase clock speeds and demand greater thermal performance, package design selection now goes well beyond a simple assessment based on physical attributes. There are tradeoffs when considering selecting a package. This article presents five primary considerations for determining the proper package: thermal performance, electrical performance, physical package attributes, substrate connectivity and package assembly considerations. Understanding the packaging design process and these five considerations can help companies requiring package design to focus their package options and minimize the design phase.
Thermal Performance Is Primary
Out of five considerations, thermal performance is the most important consideration. If a package cannot meet the device thermal performance requirements, then the package should not be considered.
To determine the basic thermal performance requirements a device will demand of a package, the package environment variables must be understood and the device's power dissipation must be known (Figure 1).
Power Dissipation. The amount of power, measured in watts, produced by a device.
Ambient Temperature. The temperature of the environment that surrounds the package.
Maximum Junction Temperature. The maximum allowable temperature measured at the top surface of the die. Typically, the junction is between the top surface of the die and a molding compound.
Based on these three components, a general Theta-ja (degree C/W) value can be calculated to provide more focus to the package selection. In addition to these three necessary components, the die size must be known as it will have a direct impact on the package's thermal performance requirements. The smaller the die size, the smaller the surface area for heat dissipation and it will not be as thermally efficient.
There are a number of options to consider that will help in choosing the appropriate package:
Air Flow. The amount of air (measured in meters per second) that will be forced over the package surface for cooling. This is accomplished by a system fan forcing air through the package environment.
Thermal Ball Matrix. On ball grid array (BGA) packages, adding a thermal ball matrix under the die provides a direct thermal dissipation transfer path from the package to the printed circuit board (PCB).
Figure 1. These three components are used to determine the general package thermal performance.
Exposed Die Attach Pads (DAP). On leaded or leadless packages, DAP can be exposed on the backside of the package to provide a thermal dissipation path from the package to the PCB.
Increase Substrate Layer Count. Increasing the layer count (i.e. from two to four layers) adds additional copper to the package and serves to improve the thermal performance.
Copper Plane Thickness. Increasing copper thickness of the power and ground planes improves thermal performance.
Heat Sink or Slugs. Use of an internally embedded slug or externally attached heat sink provides additional increases.
Filled Vias. In addition to other improvements, plugging via drill holes with thermal conductive epoxy will provide improvements.
Increase Package Size. Larger package sizes positively affect thermal performance.
After thermal constraints have narrowed down the packaging options, the electrical performance requirements further define the feasibility outcome. To understand the substrate performance requirements, it is important to know specific performance requirements and the capabilities of the substrate technology.
Figure 2. Netlist format.
Identifying Critical Signals. In many cases, critical signals will be identified with a specific clock speed and have signal impedance requirements. The substrate technology and layer stackup will be a key element in achieving the signal impedance requirement. BGA substrates have the flexibility to accommodate reference plane layers to achieve the impedance requirements. Lead frame packages do not have this flexibility.
Signal integrity. Understanding the design's signal integrity requirements such as signal impedance, differential signal routing, cross talk specifications and signal parasitic parameters (RLCG) is critical. Based on the signal integrity requirements, lead frame or substrate technologies can be investigated or eliminated from consideration.
Substrate Plating Requirements. If the substrate technology uses the electrolytic plating process, every signal will have a plating trace for the Ni/Au deposition process. For critical signals with high clock speeds, long plating traces can have a negative impact serving as antennas. Allocating signals to outside package ball locations will minimize plating trace lengths. An etch-back plating process can also be used to reduce long plating traces to small stubs.
Substrate or Lead Frame Connectivity. Minimizing critical signal path lengths by considering ball or lead locations with respect to the die pad/bond finger location will benefit the electrical performance. If the critical signals are given priority when considering the die and package design, the wire bond length can be minimized and routed signal paths can be straight and short.
Working closely with package characterization data will help guide and determine the proper substrate technology to meet the performance requirements. If the thermal and electrical performance requirements can be met, the designer can move forward to define the physical attributes of the package.
Based on the thermal and electrical assessment, the package technology options (FBGA, PBGA, QFN etc.) are clear and the remaining three considerations continue to narrow the options until the proper package and design scenario are developed.
Typically, the basic physical package attributes are defined by the customer. Attributes such as die size, desired lead or ball pitch (i.e. 1.27-mm, 1.0-mm, 0.8-mm, 0.65-mm, 0.5-mm) and required lead or ball count are based on the PCB mating and the number of total I/O pins, as well as power and ground pins. If there is an existing PCB with a set connectivity and lead / ball pitch, the options for lead / ball pitch and count are eliminated. Based on the thermal requirements, there may be an exposed DAP or center ball matrix requirement to improve thermal performance.
A package specification may specify a maximum package height requirement and JEDEC package outline to follow. Based on these inputs, the overall package size/footprint and substrate layer count (typically 2 or 4) can be solidified if thermal and electrical performance is not compromised.
During this portion of the feasibility process, cost considerations are also taken in to account. For example, the tooling availability for the proposed lead frame or BGA package could alter the cost of the package. Typically, there is no issue with lead frame packages because there are a number of standard tooled lead frames available. However, the more advanced leadless packages can be customized to meet specific design requirements thus requiring tooling. For BGAs, the package is typically custom and tooling availability (i.e. ball attach tooling, encapsulation/ mold tooling, singulation etc.) should be investigated and confirmed.
Continuing to consider cost, issues related to test such as tester and test socket availability can be identified. Also, it should be noted that the ball pitch may have cost impacts if not already defined. As the package ball pitch decreases, PCB connectivity challenges and cost can increase.
Once the package has been selected, the package connectivity can be investigated. The connectivity is the conductive path that includes the die, wire bond, BGA bond finger or lead frame lead. For a leaded package, the wire and lead is the entire conductive path. For a BGA package, the connectivity continues from the bond finger to a via location.
Figure 3. The wire loop profile concept can be arranged to minimize wire shorts.
These interconnects between die pads and lead frame leads or BGA ball locations, are a netlist. Typically, there are three approaches to this task. One, the netlist is predefined and no connectivity changes can be made. Two, the netlist is partially defined and the remaining unassigned signals can be optimally assign to a lead or ball location. Three, the netlist is not predefined and the designer is responsible for defining the package connectivity.
Regardless of what netlist option is applicable, the netlist format is crucial to a successful integration with the design tool. When properly formatted and imported into the design tool, the netlist provides intelligence to the graphics (i.e., die and lead/ball locations).
Using standard netlist formats reduces design cycle time by eliminating the need for netlist and die coordinate file formatting (Figure 2). The die and netlist connectivity will be created simultaneously and reduce database preparation time. It also eliminates the chance for netlist formatting errors. If the netlist is properly formatted, there will be no requirement for netlist manipulation to comply with required netlist format.
Another package connectivity consideration is the use of power and ground rings vs. down bonding to the package DAP. The package-to-die size ratio will determine if the use of rings or a DAP for bonding is feasible. If feasible, the ability to bond to rings or DAP allows for short, direct wire connections for power, ground or critical I/O signals. The rings or DAP can also reduce the lead/bond finger count requirement and turning and unfeasible design in to a feasible design.
In conjunction with the package connectivity, manufacturing consideration must be taken into account at the same time. If the package cannot be assembled with high yields, the design will not be successful and force the assembled package to be reworked or redesigned.
I/O Density with Respect to Die Size. As the wire density increases and the die size decreases, the wire length and wire angles will increase. With this rule in mind, the following three areas should be analyzed.
Wire Lengths. The lengths should be within the maximum wire length specified by the assembly guidelines. Long wires are susceptible to wire sagging or wire sweep during the encapsulation process.
Figure 4. Correct and incorrect wire bond sequences are shown here.
Wire angles. The wires angles have been limited by the capabilities of the wire bond equipment. More importantly, as the angle increases, the spacing decreases to adjacent wires. Large angles can potentially cause wire shorting near the die where the spacing has been minimized.
Wire Loop Profiles. Loop profiles can be varied so that the die pad density can be increased while avoiding wire shorting due to crossing (Figure 3). The maximum height and number of wire loop profiles will be limited by the thickness of the encapsulation.
Die Pad Design. It is important to review the die pad layout as a part of the feasibility. Assembly subcontractors publish die pad design rules that coincide with their wire bond machine capabilities and are based on their qualified process capabilities. Knowing these guidelines up front can save valuable time.
These guidelines include several die design parameters to consider: the linear or staggered die pad configuration; the die pad pitch; the die pad opening size; and the spacing of the corner die pads, where wire shorting is most common. In addition, if the die pad ring configuration is staggered, it is important to know the location of power and ground die pads on the die pad ring. For a BGA design with power and ground rings, down bonds from the die to the rings are short and must be located on the outside die pad row the achieve the correct wire loop profile (Figure 4).
Substrate Design Features and Clearances. Knowing the substrate vendor's manufacturable design features and clearances is essential. Vendors are constantly fine- tuning their manufacturing process and designers need to stay up to date on the latest design rules. Also, knowing which rules apply to volume production and prototype can impact the design feasibility outcome.
Key substrate design elements that are critical to most feasibility studies are the bond finger pitch and the finished bond finger top flat width. The finger pitch is directly related to I/O density and determines the bond finger top flat width. The top flat width limits are determined by the wire bond machine's positional accuracy and the wire diameter used for the build.
Other key elements that continue to shape the design include the signal trace pitch (finished trace width and space) and the drill type, (mechanical or laser) and drill diameter with respect to the via pad diameter. As the solder ball pitch is reduced, trace routing and via placement becomes more critical. Understanding the limits of the solder ball attach process and the vendor's solder mask registration capabilities will define the minimum solder ball pad diameter. The solder mask opening determines the solder ball pad diameter.
For lead frame packages, the considerations are straight forward. Since a majority of lead frames are standard, tooled and available, there are only a few considerations to review. The wire bond length and angle review is applicable, but also the DAP clearance with respect to the die size must be considered. If there are DAP down bond requirements, additional die to DAP clearance will be required as specified by the package assembly rules.
With the continued push to reduce the package footprint and improve package performance, there is more to consider than just simple physical package parameters. Designers must be aware that there is no one-size-fits-all approach to selecting an appropriate package type for your design.
The package design feasibility process must consider several complex issues. The complicated task of selecting the right package can be simplified by developing a systematic method of evaluation. Using the criteria of thermal performance, electrical performance, physical package attributes, substrate connectivity and package assembly considerations to evaluate all potential package options will help an engineer select the best package type for the design.
GREGORY PHIPPS, design manager, may be contacted at Advanced Interconnect Technologies Inc., Pleasanton, CA.; e-mail: firstname.lastname@example.org.