Issue



Wafer-level Processes are Going Backwards-compatible


12/01/2005







Whichever way you read the data or interpret the signs, modern product lifecycles are diminishing quickly enough to stretch the limits of feasibility. The technologies employed, however, are moving to a rather different drumbeat. Far from being consigned to the bone pile, tried and trusted technologies from surface mount assembly and digital electronics to the paperless office and a cashless society have, in fact, proved to be complementary to their predecessors. Some established technologies even experience an upsurge rather than dwindling death. Not only are we using more paper in our offices, we are also finding new ways to assemble through-hole components at high-speed, and applying digital FPGA philosophy to create configurable analog components.

Apply the same reasoning to the semiconductor business, and it can be concluded that the latest wafer-level packages will not vanquish the formats with which designers and assemblers are familiar. Our industry needs a broad choice of well-established packages to meet its objectives, in addition to the most modern styles.

The reasons for this are based on cost, risk, availability, and technical requirements. Consumer demand and media focus are fixated on ultra-low profile products such as flat-screen TVs, cell phones, and media players. Designers need the latest wafer-level packages to realize these devices. Alternatively, well-established electronics technologies enable everyday devices, such as simple toys and domestic appliances, to become more sophisticated, entertaining, and energy-efficient.

Wherever these products are built, designers need to ensure the lowest-cost implementation that will meet functional and environmental specifications. This will require the best possible choice of components. Therefore, package styles will not die. Millions of components will continue to ship out of semiconductor assemblers’ doors, built using the trusty leadframe, for example, while flip chip and other direct interconnect technologies continue to push the boundaries of the feasible.

What will change is the cost structure of these devices and the manufacturing methods used to build them. For a while, the packaging industry focused on replacing cumbersome construction techniques to reduce overheads, as average die-area-per-circuit-element has reduced. Alongside this drive toward miniaturization, another significant factor has been at work. Component vendors face an inescapable imperative to reduce the complexity, cycle time, and capital cost involved in performing assembly processes associated with these technologies, such as attaching bond wires, and individually dispensing materials, such as adhesives, thermal interface materials, and die attach epoxies.

The techniques developed to streamline and cost-reduce the latest flip chip and wafer-level packaging processes are also directly relevant to the package styles these new constructions were intended to streamline. Some of these leading-edge techniques and approaches are feeding back into legacy package styles, thereby extending choices for component designers.

Wafer-level processing, aided by low, entry-cost enabling technologies such as high-accuracy mass-imaging, has played a large role in opening up the non-captive packaging sector. Specialist wafer-processing houses have grown by taking many of the tasks the semiconductor brand owners were unable to perform cost-effectively to support commercialization of next-generation chip scale packages. Now that this model is proven, brand owners expect the specialists to take on more of the expediting. To save further investment in expensive equipment, process expertise, and training necessary to perform legacy processes-such as die attach using wet epoxy materials-the non-captive sector must re-apply some of their wafer-level techniques to traditional packages. We are already seeing leading wafer specialists move in this direction.

This cross-fertilization has tremendous potential. The enabling technologies for high-volume, commercial assembly of chip scale packages have streamlined and simplified production, enabled higher throughput and yield, and reduced training overheads and capital expenditure. These benefits will deliver cost savings and performance enhancements in legacy package styles.

The non-captive sector will be happy to take on more processes offloaded by their customers-the semiconductor brand owners. They will do it better, faster, and cheaper through higher use of versatile, next-generation equipment sets that support rapid changeovers between numerous materials and processes. There will be valuable enhancements to packages that have changed little for generations, as a natural result of integrating new assembly processes. Older packages - and particularly power packages, where miniaturization is opposed by the demand to maximize thermal and electrical conductivity - will be given new, longer legs. Allowing traditional package styles to be produced according to 21st-century throughput and cost metrics will result in greater choice for package designers.

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RICH HEIMSCH, president, may be contacted at DEK International, Geroldstrasse 28, 4 Stock, CH-8005, Zurich, Switzerland; 41 1274 8025; E-mail: rheimsch@dek.com.