Issue



Solder Bumping for Emerging Wafer-level Packages


12/01/2005







Expanding Technologies Match Demand

BY MARK WHITMORE

Component designers are seeking to use wafer-level packaging (WLP) in as many applications as possible; and the technologies to support building WLPs are maturing quickly. One crucial process is wafer bumping, where the techniques available are already displaying a distinct trend toward a “horses for courses” situation: a perennial indicator of maturity. But the range of courses continues to expand, as component designers in disciplines including power and opto are now aggressively transitioning to WLP.

Comfortable Coexistence?

There are several established techniques for wafer bumping, each having their own strengths and weaknesses. Stud bumping using gold wire, as well as gold plating with either electrolytic or electroless gold, is mainly used for low-pin-count packages up to around 40 pins. Applications include chip-on-glass, chip-on-flex, and RF modules, but high materials costs and long cycle times make these techniques unsuitable for packages with large numbers of I/Os. Placement and reflow of preformed solder balls may be used for packages with both high and low pin counts. The two most common methods are electroplating of solder, or solder paste printing and reflow using a high-accuracy mass-imaging platform.

An advantage of solder paste printing is the low capital cost of the equipment. This enabled a large number of wafer-bumping houses to enter the market to service semiconductor vendors’ needs as demand for wafer-bumping services grows quickly with increasing commercial acceptance of WLPs. The majority of wafer-bumping houses prioritize printing capability, and some also offer one or more alternative techniques. Many in the industry expect printing to dominate the majority of wafer-bumping applications.

Wafer-level Power MOSFETs

However, emerging applications such as WLP for vertical power MOSFETs for mobile and portable applications require a relatively small number of bumps. It is critical that these bumps have a large cross-sectional area to save die free package resistance; a major contributor to the device’s R(DS)ON parameter. This affects the efficiency and battery life of the end product, whether it is a cellular phone handset, PDA, media player, or any one of a number of consumer instruments. Solder ball attachment, using solder balls up to 0.5-mm diameter, allows deposition of a high volume of solder to maximize the interconnect cross section within the natural limits imposed by the bump pitch.

A recent European project has developed solder ball attach techniques to allow WLP to be applied to vertical power MOSFETs, enabling a 75% reduction in package footprint while lowering die-free package resistance, compared to the standard SO style package. The project, backed by the European Commission*, aimed to create next-generation devices in wafer scale packages for wireless handheld applications in LAN environments, including both the SoC and power amplifiers required to implement a highly miniaturized baseband stage for short- and mid-range wireless networking.

Wafer-level techniques have been applied successfully to horizontal devices, but vertical topology enables a reduced footprint, which is ideal for mobile applications. The challenges involved in creating wafer-level vertical power devices lie in re-routing backside contacts to the front of the wafer before bumping to create the WLP. Re-routing is achieved using plated, filled vias that demand a thin wafer to achieve a suitable aspect ratio. By specifying vias of 300-µm diameter, the project implied a wafer thickness of 150 µm to maintain an aspect ratio of 2:1.

The project presented two challenges to the solder ball attach process. First was to demonstrate high repeatability and yield at 500-µm bump pitch with lead-free solder balls. Second was to ensure that thin, 150-µm wafers could be bumped and subsequently passed on to reflow without damage to the wafer or losing ball alignment due to flexing of the wafer.

To complete the development of the required WLP for the MOSFET power amplifier, the project’s consortium partners developed a solder ball attach process for spheres at a diameter of 300 µm ± 10 µm at 500-µm pitch onto 6-in. diameter wafers. Preliminary experiments first proved the techniques using wafers of 680-µm nominal thickness before moving on to establish successful bumping on the thinner, 150-µm wafers.


Figure 1. Ball placement equipment set.
Click here to enlarge image

Two in-line printing machines are required for a solder ball attach process (Figure 1). The first machine deposits flux onto the wafer bond pads. A second machine configured to place solder spheres on the pads then completes the final stage of the process before the wafers are reflowed.

The first machine loads and aligns the wafer using a vision recognition system, and then prints flux onto the under-bump metallurgy. The wafer is then transported to the second machine, while the first machine performs an automated under stencil cleaning process. The second machine loads the fluxed wafer, aligns it to the stencil, and brings it into contact with the stencil. The ball placement head then passes over the top of the stencil, simultaneously separating the spheres into a single layer while applying a small positive force to push the spheres through the apertures. This action ensures good contact between the spheres and the flux medium, helping to reduce movement of the spheres with subsequent handling. One or more such passes can be performed to ensure all apertures are filled. The project has established that two passes at an excursion speed of 10 mm/s can result in ball placement yield above 99.9%.

The wafer, with the solder balls attached, is then lowered away from the stencil at a controlled, programmable speed and transported to a reflow oven, so two stencils are required to perform a complete solder ball attach process. The flux stencil can use a standard stencil manufacturing technology, such as electroform or laser cutting. For the ball placement stage, a “hybrid” stencil technology comprising two layers is necessary to create a stand-off that prevents stencil apertures from becoming contaminated with flux from the first printing process. The main body of the stencil contains the apertures through which the spheres are placed. The second layer - the stand-off layer - is bonded to the bottom of the stencil.

The process developed for the project employed a 50-µm thickness screen with 200-µm diameter apertures for flux printing and a hybrid stencil of 300-µm total thickness for ball printing.

Results

In addition to the large volume of solder that can be deposited, another advantage of this process is that the volume of the solder ball is not diminished after reflow. This leads to greater repeatability, thereby enabling a more uniform bump height in each completed package.

The project, which deposited 300-µm ± 10-µm lead-free solder balls at 500-µm pitch on a 150-µm thick wafer, demonstrated a highly repeatable bump height of 260 µm (figure 2). Bump yield using this process was above 99.9%.


Figure 2. 150-µm thin reflowed wafer with vias, 500-µm ball pitch, and 260-µm bump height.
Click here to enlarge image

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Interchangeable Processes

The project has proven the value of solder ball attachment as a practical, high-yield bumping technique for wafer-level power devices. Adoption of solder ball processes is likely to increase as production of such packages ramps up. A benefit to wafer-bumping houses already equipped with solder paste printing capability is that the majority of printers for wafer bumping can easily be changed over to solder ball attach and back again. These businesses can begin cost-effective assembly of wafer-level power packages and other array package types that are best served by solder ball attachment. This also will accelerate the return on their initial investment in capital equipment.

Blurring Boundaries

Growth in the number of wafer-bumping specialists who are printing solder paste to service world demand for WLPs is engendering widespread familiarity with mass imaging in semiconductor packaging. However, large EMS businesses are also now entering the WLP arena. Continued blurring of the boundaries between package and board, and between the packaging and assembly processes obliges these enterprises to position themselves to offer wafer-level and chip scale capabilities to their customers. Of course, they are already familiar with precision screen printing, having used it for many years to deposit solder paste ahead of component placement. Moving into wafer-level processing using print-based technologies is a relatively small step.

Reference

*The European-funded IST-2000-30006 “Blue WHALE” project partners included Philips Applied Technologies (The Netherlands), DEK Printing Machines Ltd. (UK), Dimes, a subsidiary of Delft University of Technology (The Netherlands), Shellcase Ltd. (Israel), and TU Berlin (Germany).

MARK WHITMORE, advanced technologies group, may be contacted at DEK, 11 Albany Road, Granby Road Industrial Estate, Weymouth, Dorset, DT4 9th; 44 0 1305 208 302; e-mail: mwhitmore@dek.com.