Issue



Automating IC Package Design


11/01/2005







BY JOHN ISAAC

With advances in semiconductor fabrication driving into the nanometer range comes more pressure on IC packaging technologies to meet the needs of new devices. This manifests itself in a growing number of I/Os on a chip, faster edge rates, the emergence of asynchronous SERDES (serializer/deserializer) I/O and interconnect standards, more power/ground pins, and necessitates a more controlled design flow.

The wireless industry also drives the need for complete systems within a package, including custom ASICs and off-the-shelf ICs; mixed signal, RF, and digital circuitry on the same substrate; and pushes a reduction in real estate and time-to-market.

Systems-in-package (SiPs) require integration of multiple interconnect and device technologies on a single substrate. Stacked die, while facilitating incredible design densities, pose challenges with localized wire bonding and trace routing density.

Sequential build-up substrate technologies, which enable connection to high-density IC packages, now require unique trace/via interconnect constraints. Embedded passive and active components, which significantly reduce product size, need advanced footprint creation, placement, and analysis capabilities.


Figure 1. The design of an IC package.
Click here to enlarge image

Integrating RF circuitry on the package substrate eliminates a discrete package and reduces product size and complexity, but creates design definition, layout, and system simulation challenges.

Sophisticated packaging design solutions once considered cutting-edge or deemed too costly are moving into the mainstream to meet the needs of these market drivers. Functionality now required in the package design solution includes direct integration of the IC and package design; automation of package routing; complex wire bond, flip chip, stacked die, and other mounting design rules; passive resistor and capacitor synthesis and placement; high-speed delay, signal and power integrity analysis; extraction and model building of the 3-D wire bonds and package interconnect; thermal and mechanical stress analysis due to higher temperatures; and manufacturing rules checking.

Engineers require a robust set of features and functionality with the flexibility to address multiple technologies and advances in the market when designing these next-generation substrates. Three-dimensional wire bonding for stacked die, connectivity management for SiP design, and power delivery analysis for chip-level modeling are among the capabilities needed to form the foundation for the new tools, which also must reflect changes in design methodologies. Some level of chip/package, and even chip/package/board co-design, is being implemented by OEMs focused on design optimization and reduced time-to-market. The goal is to lower sky-rocketing packaging costs; reduce design complexity via I/O planning between package and chip; optimize performance at the system level; eliminate costly design re-spins due to discontinuities in the design flow; reduce the number of PCB layers required to escape high-pin-count BGAs; and reduce time-to-market by supporting concurrent design.


Figure 2. IC/Package/PCB design collaboration.
Click here to enlarge image

For the most part, OEMs use spreadsheet applications such as Microsoft Excel to manage connectivity and I/O planning across multiple domains. A better solution is an I/O management capability that integrates the IC, the package, and the PCB systems design, and allows designers in all three domains to perform tradeoffs and analysis of the best chip and package I/O assignments and automatically communicate those to the other domains and solutions. This common thread can facilitate concurrent design collaboration among the disciplines.

High-end EDA vendors have entered the picture and provide the solutions needed for these advancing challenges. They can provide the required functionality in all three domains (IC, package, and PCB) and the integration of that functionality to form a technology-rich silicon-to-systems solution useful by IC suppliers, package suppliers, and vertically integrated OEMs.

Click here to enlarge image

JOHN ISAAC, director of systems market development, Systems Design Division, may be contacted at Mentor Graphics, 1811 Pike Rd., Longmont, CO 80501; 720/494-1270; john_isaac@mentor.com.