Issue



Lead-free WLCSP Qualification


11/01/2005







A Consumer Electronics Case Study

BY CURT ERICKSON AND SCOTT POPELAR

Legislation eliminating lead from electronics systems necessitated a search for alternative materials to fit in existing assembly infrastructure, meet cost targets, and equal or surpass current reliability requirements. This article describes one company’s* lead-free wafer bumping processes, including under-bump metallurgy (UBM) and Sn/Ag/Cu (SAC) alloy evaluation. Bump performance is covered at wafer-level and board-level qualification testing in a cell-phone application.

The most economical method of creating flip chip and wafer-level chip scale packages (CSPs) is electroless Ni/immersion Au as the UBM and stencil-printed solder paste, or by dropping solid diameter solder spheres. Development and qualification of lead-free alloys used this same UBM system in 2001. To create a solderable Ni surface on native aluminum or copper traces present on today’s integrated circuits (ICs), a series of wet chemistries are used that clean, selectively activate, and nucleate exposed metal on wafers. Electroless Ni is deposited on metal I/O pads to a thickness determined by temperature and time in the bath. A flash of immersion gold is deposited as an oxide barrier to aid in the subsequent reflow process.

Stencil printing discrete solder paste deposits on I/O pads and reflowing to form a metallurgical bond creates solder bumps. A stencil can also deposit flux. A second matching stencil delivers a solid diameter sphere to each I/O pad, and reflow creates a metallurgical bond.

Lead-free Solder Qualification at Wafer Level

It is crucial that the Sn/Ni intermetallic not reach the base IC Al or Cu pad before end of life. Shear load to failure needs to be sufficient based on material sets and environmental mission profile. These two elements are evaluated at wafer-level by shear testing and multiple reflow testing. Figure 1 shows a plot of bump shear load of lead-free, eutectic Sn/Pb and high-lead solder alloys as a function of the number of reflow exposures.


Figure 1. Shear test plot of various solder alloys as a function of reflow exposure.
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Multiple exposures of solder alloy to melt temperatures do not negatively impact shear performance of solder bumps. This is a necessary first step for proceeding with lead-free alloy investigation.

The next wafer-level evaluation determines a robust process window of Ni UBM thicknesses. Figure 2 shows a plot of bump shear load for various UBM thicknesses as a function of number of reflow exposures.


Figure 2. Shear test plot of various Ni thickness UBMs as a function of reflow exposure.
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This set of plots indicates that absolute solder-bump shear load to failure of lead-free solder alloys exceeds that of two lead-based alloys tested. Even with electroless Ni deposits as thin as 1 µm, they are sufficient to survive 10 reflow cycles. This data was encouraging enough to pursue bumping devices for board-level reliability testing.

Board Assembly Overview

Two devices were bumped, assembled, and subjected to various reliability tests in cell-phone applications. Figures 3 and 4 show two daisy-chain test devices laid out on 500-µm pitch with a reflowed bump height of 250-µm nominal. This configuration is common in the cell-phone industry because it allows for placement of bare-die components in a similar fashion to standard plastic packaged SMT parts, and alleviates the need for a post-reflow underfill.


Figure 3. 24-pin device layout.
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Figure 4. 11-pin device layout.
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Mechanical makeup of test boards has a significant impact on the outcome of reliability testing. Circuit boards used in this evaluation represent typical, cost-effective design rules and material sets and, at times, worst-case mechanical configurations. Details of boards used for various tests are described here:

Boards for PCT, THT, HTS, and Push Test on Board

  • For all these tests, samples were mounted on 1.6-mm thick, FR4 single-layer PCBs.
  • Layout is according to the top layer of the bend-test board.
  • Final surface is electroless NiAu (Ni: 3 to 5 µm, Au: 0.2 to 0.3 µm)

Boards for Bend Test, Drop Test, and TCoB

  • These tests use special boards.
  • Boards are 1-mm thick and have 4 metal layers.
  • Final surface is Cu-OSP.

In all cases, die were attached to boards by printing additional lead-free paste onto boards, placing bumped die into the paste and reflowing. No underfill was used.

Alloy Qualification at Board Level

A full-blown, board-level reliability evaluation was conducted and actual results are summarized here:

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The lead-free system passed various tests, and met all standard testing conditions and acceptability requirements used by the cell-phone industry.

Conclusion

It is uncommon to find an assembly system that performs well in both temperature-cycle testing and drop testing. The lead-free interconnect system survived both thermally and mechanically induced strains.


Figure 5. Weibull plot of TC data.
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The industry is searching for a lead-free solder alloy alternative that will fit into the existing assembly infrastructure; meet cost targets; and equal or surpass the current reliability requirements. While the cost of lead-free alloys is somewhat higher than leaded versions, it is not cost-prohibitive, and is expected to decrease as lead-free becomes mainstream.

CURT ERICKSON, president, and SCOTT POPELAR, director of engineering, may be contacted at IC Interconnect, 1025 Elkton Drive, Colorado Springs, CO 80907; 719/533-1030, Ext. 12; E-mail: cerickson@ icinterconnect.com; 719/533-1030, Ext. 11; E-mail: spopelar@icinterconnect.com.