Materials and Methods for IC Package Assemblies
Packaging Design Review
BY JOSEPH FJELSTAD
he IC is either the pinnacle or the base of electronics hierarchy, and both positions are arguably right. The IC represents the pinnacle in terms of electronic device (i.e. transistor) density, but it is also the starting point, the fundamental building block, and foundation for most of today’s electronic systems. As such, ICs are not monolithic or fundamental electronic structures. IC types differ significantly (analog, digital, RF, sensor, etc.), as do their packaging needs and requirements differ. This article provides an overview of IC packaging technology, exploring, in broad-brush fashion, the materials and processes used to create these indispensable structures.
While IC physical constructions, applications, and I/O counts may vary widely, the roles and functions of IC packages are fewer in number and more consistent in purpose. The IC package has several roles to play as “keeper of the chip,” but it has two primary and fundamental functions: 1) the IC package protects the die from physical damage and 2) redistributes the I/O to a more manageable pitch in assembly. There are, as well, a number of potential secondary roles, such as providing a structure more amenable to standardization, providing a thermal path away from the die, providing protection from the potential of soft errors due to alpha particles, and providing a structure more easily disposed to electrical test and burn-in. The package can also serve to interconnect multiple ICs both directly to each other using standard interconnection technologies, such as wire bonding, and indirectly using interconnection pathways provided on the package, such as those used in hybrid packages and MCMs and currently in system-in-package (SiP) and other methods covered under the broader concept of volumetric system miniaturization and interconnection (VSMI).
With the increased interest and deployment of microelectromechanical systems (MEMS) devices and lab-on-chip devices, the package provides additional capability, such as localized access to the environment, a requirement for pressure difference, or as required for chemical or atmospheric condition analysis. There is also growing interest and activity in the development of optoelectronic packages to address the needs of this increasingly important area of activity. There has been a significant ground shift in recent years relative to the importance and expanding role of IC packaging, to the point that the IC package has achieved a measure of parity in terms of importance with the IC itself. This is because, in many cases, the performance of the IC is gated by the IC package. As a result, a great deal of attention is being devoted to improving IC packaging technology to meet these challenges.
IC Packaging Families
While there are many ways to codify IC packages, they can be most broadly separated and defined by their basic construction. Using these criteria, the two primary categories are leadframe-type packages and substrate-type packages. The latter category can then be further subdivided into organic-laminate and ceramic-base materials. There is now also a package product family concerned with the assembly of ICs on the wafer called wafer-level packaging (WLP). Here, the packaging elements typically are constructed on the face of the wafer, resulting in a true chip-size package.
Following the definition of fundamental structure, there is the matter of how the package is presented to the next level of interconnection. For example, many legacy IC packages, such as the leadframe and the dual in-line package (DIP), are designed for either pin-in-hole solder assembly, while others, such as the pin-grid array (PGA), are designed for socketing. Still others, such as the compliant-lead-type leadframe packages, typified by quad flat pack (QFP), the leadless-type leadframe package, and the near chip-size quad flat no-lead (QFN) package, are designed for surface mounting (Figure 1).
Figure 1. IC packages come in a variety of sizes shapes and pin counts to meet the varied needs of both ICs and systems.
While the QFP and QFN are representatives of peripherally leaded packages, there are also area array packages. The area array format for IC package I/O terminations is growing in popularity due to its inherent ability to handle high I/O without sacrificing performance and its natural area conservancy. Ball grid array (BGA) packages are emblematic of this type of package. Due to these benefits, BGAs are found in a range of formats from tiny chip scale and wafer-level packages to larger IC packages having hundreds to thousands of I/Os. BGA packages are commonly made using organic laminate substrates, owing to the large, cost-effective manufacturing infrastructure available for their construction. BGAs are also a common format for the growing family of stacked-chip, multichip, and stacked-package structures. Multichip packages are viewed as a practical alternative to system-on-chip (SOC) solutions. There are also newly proposed families of products based on stair-stepped packages and two-surface interconnection concepts (Figure 2).
Figure 2. Examples of unusual BGA constructions (courtesy SiliconPipe).
IC Package Materials and Assembly Review
Materials used in the construction of these various IC packages are of great importance. Their physical, electrical, and chemical properties establish the foundation of the package, and ultimately its performance limits. Leadframe and laminate-based package structures have obvious physical differences; however, there is much commonality in terms of their performance needs relative to their respective material properties. A point-by-point review of the constituent elements will help to demonstrate the variety of choice and the complexity of need requirements.
Leadframe materials are a logical starting point, as leadframe products remain the dominant IC package format. Leadframes are mostly used for wire-bond interconnected die and a wire-bondable finish, such as silver or gold, is plated onto the area referred to as “inner bond-lead area” using a spot-plating method. This controls costs because noble metals are not easily bonded to encapsulants.
The metal used for IC lead frames typically is limited to one of a few choices based on the needs of the package. For ceramic packages, the common choice is Alloy 42 or Iconel because these alloys are closely matched in CTE to commonly used ceramic materials, which is an important requirement due to the brittleness of the ceramic. However, depending on size, the low CTE can have a deleterious effect on reliability on the final assembly for surface mounted components. This is due to its mismatch to most standard PCB substrates. While higher modulus, lower CTE metals have worked well as lead frames for both ceramic and plastic DIP-type packages, copper leadframe materials have proven a better choice for surface mount plastic packages choice due to their compliance and ability to protect the solder joint. Copper also has the advantage of greater conductivity.
Lead finish for next-level assembly is a matter of increasing importance as the industry transitions to meet the demands of the looming European legislation. This topic has been the subject of countless papers over the last few years. The primary emphasis is on finding alternatives to the long-used and well-understood tin-lead solders. Due to heavy competition and position marketing by prospective suppliers, there is no single solution, and it is likely that there will be much confusion on the matter of lead finishes for many years to come.
Die-attach materials are used to bond the die to the substrate. While seemingly a simple task, the requirements can be varied, depending on the application. In most cases, die attach is used for face-up wire-bond assembly. It is also thermally conductive, and in some cases, electrically conductive as well. To avoid hot spots on the die, the die-attach process should ensure that there are no voids in the attach material. As chip power continues to rise, this will be more important.
Figure 3. IC packages of all types share some common features. Most notable are encapsulation and a means to redistribute the I/O to a more useful configuration.
Die-attach materials come in liquid and film formats. They are designed and intended not to outgas. This is due to the concern that redeposition of any potentially outgassed product on to bond pads could degrade wire-bond quality. The die-attach material has a second function as a stress buffer to protect the die from fracture due to CTE mismatch with the substrate to which it is bonded. The die-attach adhesive, if properly chosen and applied, can also provide the secondary benefit of assuring the reliability of I/O redistributed beneath the chip in chip scale package structures. Die-attach materials have also been modified for flip chip interconnection. In such applications, the IC is normally bumped and the adhesive has a conductive particle distributed within it. This type of die-attach material construction is also called an anisotropic conductive adhesive.
Turning to the matter of wire-bond assembly, there are three basic types of wire-bond technology: thermo-compression bonding, thermosonic ball bonding, and room-temperature ultrasonic wedge bonding; however, only the latter two types are in wide use today. Gold wire is common and typically used for thermosonic wire bonding. Copper wire is another choice, but requires a nitrogen-rich assembly environment, while aluminum wire is typical for low-cost wedge bonding.
Laminate materials used for IC packaging are an alternative to the leadframe, and are used in situations where I/O counts are high or where higher performance levels are sought. Laminates have been used since the late 1970s for chip-on-board applications. In fact, when one looks critically at chip-on-board, it is clear that it has all of the basic elements of a package, and is fundamentally “packaging in-situ.” That aside, laminate package structures are used today and are an important IC packaging medium that serves as a low-cost alternative to the thick- and thin-film ceramic substrates. The newer, higher-temperature organic laminates are favored, not only because they are lower cost, but also because they have better electrical characteristics (e.g. lower dielectric constant).
Encapsulants are the final constituent of an IC package. While the leadframe serves to redistribute the I/O from the fine pitch of the chip terminations primarily, the encapsulant provides other benefits. Its main role is protecting the chip and the delicate bond wires from physical damage and the environment. Encapsulants must be applied with care and precision to prevent wire sweep, which can result in shorting wires to one another.
There are three basic types of encapsulant materials used for IC packages. The first is epoxy and epoxy blends. As the most common type of resin used in structural-engineering applications, epoxies are also the most commonly used organic-resin encapsulant materials in use today. Epoxies offer a beneficial mix of properties and thermal performance at a relatively low cost.
Table 1. Examples of materials used in IC packaging. Note that IC packages of the basic family groups use many of the same materials in their construction.
Silicone materials are another popular encapsulant for IC chips. Because these resins are silicon rather than carbon-based, they are not considered organic resins, even though some of their processing and curing regimens are similar to organic resins. Silicone resins are of two primary types: solvent-based and room-temperature-vulcanizable (RTV). Curing is accomplished by different mechanisms, depending on the type. RTVs are cured either by exposure to moisture (room humidity) or by catalyst addition. In contrast, solvent-based silicones are most commonly cured thermally after evaporation of the solvent. Silicones are quite flexible over a range of temperatures (from -65° to 150°C) making them a popular choice for CSPs seeking compliance.
The last of the three basic encapsulants is polyimide. Polyimides are used less often in IC packaging as an encapsulant. They are fairly common in die-attach adhesive formulations. Polyimide resins have a high-temperature capability, making them acceptable for high-temperature.
Encapsulants are facing a reformulation challenge, a result of EU mandates for alternatives to traditional solders. The higher-temperature requirements of high tin solders that meet the legal requirements have resulted in increased moisture sensitivity. In accordance with JEDEC moisture-sensitivity requirements, most current materials have been de-rated by two levels. More pre-baking of packages will be required to drive-out moisture and prevent popcorning, or explosive outgassing of entrapped moisture during reflow.
This brief review highlights the pivotal role IC packaging plays in the electronics industry hierarchy, and demonstrates how it is arguably the most important element in electronic system design. Package choices are many growing to keep pace with the expanding variety of I/O counts and performance needs. This offers a solution to those seeking answers to difficult problems. It is, however, a curse to those seeking the solace of monolithic standards. Indeed, it is foreseeable that there may come a time when standards will become less important, especially as the concepts of co-design of IC, package, and substrate become more prevalent. While customization is likely to become more common, the materials and processes used to create these vitally important links in the electronics chain likely will remain relatively constant. The door will remain open only to those improvements that offer significant benefits.
*For a complete list of references, please contact the author.
JOSEPH FJELSTAD, founder and principal, may be contacted at SiliconPipe, Inc., 992 DeAnza Blvd., San Jose, CA 95129; 408/973-1744, e-mail: email@example.com.